tech_axcel.vhd

ARM7的源代码

    rftype : integer := 1;
    abits : integer := 8; dbits : integer := 32; words : integer := 128
  );
  port (
    rst      : in std_logic;
    clk      : in std_logic;
    clkn     : in std_logic;
    rfi      : in rf_in_type;
    rfo      : out rf_out_type);
end;

architecture rtl of axcel_regfile_iu is
component axcel_ssram 
  generic (abits : integer := 16; dbits : integer := 36);
  port (
    wa, ra       : in  std_logic_vector(15 downto 0);
    wclk, rclk   : in  std_logic;
    di           : in  std_logic_vector(dbits -1 downto 0);
    do           : out std_logic_vector(dbits -1 downto 0);
    width        : in  std_logic_vector(2 downto 0);
    ren, wen     : in  std_logic
   ); 
end component;
signal wen, gnd : std_logic;
signal width : std_logic_vector(2 downto 0);
signal depth : std_logic_vector(4 downto 0);
signal wa, ra1, ra2 : std_logic_vector(15 downto 0);
signal di, q1, qq1, q2, qq2 : std_logic_vector(35 downto 0);
signal ren1, ren2 : std_logic;
constant xbits : integer := 32/(2**(abits-7)); 
begin
  width <= "101" when abits <= 7 else
           "100" when abits = 8 else
           "011" when abits = 9 else
           "010" when abits = 10 else
           "001" when abits = 11 else
           "000";

  wen <= not rfi.wren; gnd <= '0';
  wa(15 downto abits) <= (others =>'0');
  wa(abits-1 downto 0) <= rfi.wraddr(abits-1 downto 0);
  ra1(15 downto abits) <= (others =>'0');
  ra1(abits-1 downto 0) <= rfi.rd1addr(abits-1 downto 0);
  ra2(15 downto abits) <= (others =>'0');
  ra2(abits-1 downto 0) <= rfi.rd2addr(abits-1 downto 0);
  di(35 downto dbits) <= (others =>'0');
  di(dbits-1 downto 0) <= rfi.wrdata(dbits-1 downto 0);
  rfo.data1 <= q1(dbits-1 downto 0);
  rfo.data2 <= q2(dbits-1 downto 0);
  ren1 <= not rfi.ren1;
  ren2 <= not rfi.ren2;

  rt1 : if RFIMPTYPE = 1 generate
    a7 : if abits <= 7 generate
      u0 : axcel_ssram
      generic map (abits => abits, dbits => 32) 
      port map ( ra => ra1, wa => wa, di => di(31 downto 0), wen => wen,
      width => width, wclk => clkn, ren => ren1, rclk => clkn, do => q1(31 downto 0));
      u1 : axcel_ssram
      generic map (abits => abits, dbits => 32) 
      port map ( ra => ra2, wa => wa, di => di(31 downto 0), wen => wen,
      width => width, wclk => clkn, ren => ren2, rclk => clkn, do => q2(31 downto 0));
    end generate;
    a8to12 : if abits > 7 generate
      agen : for i in 0 to (dbits+xbits-1)/xbits-1 generate
        u0 : axcel_ssram
        generic map (abits => abits, dbits => xbits) 
        port map ( ra => ra1, wa => wa, di => di(xbits*(i+1)-1 downto xbits*i),
           wen => wen, width => width, wclk => clkn, ren => ren1, rclk => clkn,
           do => q1(xbits*(i+1)-1 downto xbits*i));
        u1 : axcel_ssram
        generic map (abits => abits, dbits => xbits) 
        port map ( ra => ra2, wa => wa, di => di(xbits*(i+1)-1 downto xbits*i),
           wen => wen, width => width, wclk => clkn, ren => ren2, rclk => clkn,
           do => q2(xbits*(i+1)-1 downto xbits*i));
      end generate;
    end generate;
  end generate;

  rt2 : if RFIMPTYPE = 2 generate
    a7 : if abits <= 7 generate
      u0 : axcel_ssram
      generic map (abits => abits, dbits => 32) 
      port map ( ra => ra1, wa => wa, di => di(31 downto 0), wen => wen,
      width => width, wclk => clk, ren => ren1, rclk => clkn, do => q1(31 downto 0));
      u1 : axcel_ssram
      generic map (abits => abits, dbits => 32) 
      port map ( ra => ra2, wa => wa, di => di(31 downto 0), wen => wen,
      width => width, wclk => clk, ren => ren2, rclk => clkn, do => q2(31 downto 0));
    end generate;
    a8to12 : if abits > 7 generate
      agen : for i in 0 to (dbits+xbits-1)/xbits-1 generate
        u0 : axcel_ssram
        generic map (abits => abits, dbits => xbits) 
        port map ( ra => ra1, wa => wa, di => di(xbits*(i+1)-1 downto xbits*i),
           wen => wen, width => width, wclk => clk, ren => ren1, rclk => clkn,
           do => q1(xbits*(i+1)-1 downto xbits*i));
        u1 : axcel_ssram
        generic map (abits => abits, dbits => xbits) 
        port map ( ra => ra2, wa => wa, di => di(xbits*(i+1)-1 downto xbits*i),
           wen => wen, width => width, wclk => clk, ren => ren2, rclk => clkn,
           do => q2(xbits*(i+1)-1 downto xbits*i));
      end generate;
    end generate;
  end generate;
end;

-- co-processor regfile
-- synchronous operation without write-through support
LIBRARY ieee;
use IEEE.std_logic_1164.all;
use work.leon_config.all;
use work.leon_iface.all;
entity axcel_regfile_cp is
  generic ( 
    abits : integer := 4; dbits : integer := 32; words : integer := 16
  );
  port (
    rst      : in std_logic;
    clk      : in std_logic;
    rfi      : in rf_cp_in_type;
    rfo      : out rf_cp_out_type);
end;

architecture rtl of axcel_regfile_cp is
component axcel_ssram 
  generic (abits : integer := 16; dbits : integer := 36);
  port (
    wa, ra       : in  std_logic_vector(15 downto 0);
    wclk, rclk   : in  std_logic;
    di           : in  std_logic_vector(dbits -1 downto 0);
    do           : out std_logic_vector(dbits -1 downto 0);
    width        : in  std_logic_vector(2 downto 0);
    ren, wen     : in  std_logic
   ); 
end component;
signal wen, gnd : std_logic;
signal width : std_logic_vector(2 downto 0);
signal wa, ra1, ra2 : std_logic_vector(15 downto 0);
signal di, q1, q2 : std_logic_vector(35 downto 0);
signal ren1, ren2 : std_logic;
begin

  width <= "101";
  wen <= not rfi.wren; gnd <= '0';
  wa(15 downto abits) <= (others =>'0');
  wa(abits-1 downto 0) <= rfi.wraddr(abits-1 downto 0);
  ra1(15 downto abits) <= (others =>'0');
  ra1(abits-1 downto 0) <= rfi.rd1addr(abits-1 downto 0);
  ra2(15 downto abits) <= (others =>'0');
  ra2(abits-1 downto 0) <= rfi.rd2addr(abits-1 downto 0);
  di(35 downto dbits) <= (others =>'0');
  di(dbits-1 downto 0) <= rfi.wrdata(dbits-1 downto 0);
  rfo.data1 <= q1(dbits-1 downto 0);
  rfo.data2 <= q2(dbits-1 downto 0);
  ren1 <= not rfi.ren1;
  ren2 <= not rfi.ren2;

  u0 : axcel_ssram
  generic map (abits => abits, dbits => 32) 
  port map ( ra => ra1, wa => wa, di => di(31 downto 0), wen => wen,
  width => width, wclk => clk, ren => ren1, rclk => clk, do => q1(31 downto 0));

  u1 : axcel_ssram
  generic map (abits => abits, dbits => 32) 
  port map ( ra => ra2, wa => wa, di => di(31 downto 0), wen => wen,
  width => width, wclk => clk, ren => ren2, rclk => clk, do => q2(31 downto 0));

end;

LIBRARY ieee;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use work.leon_config.all;
use work.leon_iface.all;
entity axcel_syncram is
  generic ( abits : integer := 10; dbits : integer := 8 );
  port (
    address  : in std_logic_vector((abits -1) downto 0);
    clk      : in std_logic;
    datain   : in std_logic_vector((dbits -1) downto 0);
    dataout  : out std_logic_vector((dbits -1) downto 0);
    enable   : in std_logic;
    write    : in std_logic
   ); 
end;

architecture rtl of axcel_syncram is
component axcel_ssram 
  generic (abits : integer := 16; dbits : integer := 36);
  port (
    wa, ra       : in  std_logic_vector(15 downto 0);
    wclk, rclk   : in  std_logic;
    di           : in  std_logic_vector(dbits -1 downto 0);
    do           : out std_logic_vector(dbits -1 downto 0);
    width        : in  std_logic_vector(2 downto 0);
    ren, wen     : in  std_logic
   ); 
end component;

signal wen, gnd : std_logic;
signal a : std_logic_vector(15 downto 0);
signal d, q : std_logic_vector(35 downto 0);
signal ren  : std_logic;
constant xbits : integer := 32/(2**(abits-7)); 
signal width : std_logic_vector(2 downto 0);
begin
  width <= "101" when abits <= 7 else
           "100" when abits = 8 else
           "011" when abits = 9 else
           "010" when abits = 10 else
           "001" when abits = 11 else
           "000";
  wen <= not write; gnd <= '0';
  a(15 downto abits) <= (others =>'0');
  a(abits-1 downto 0) <= address(abits-1 downto 0);
  d(35 downto dbits) <= (others =>'0');
  d(dbits-1 downto 0) <= datain(dbits-1 downto 0);
  dataout <= q(dbits-1 downto 0);
  ren <= '0';

  a7 : if abits <= 7 generate
    u0 : axcel_ssram
    generic map (abits => abits) 
    port map ( ra => a, wa => a, di => d, wen => wen, width => width,
	 wclk => clk, ren => ren, rclk => clk, do => q);
  end generate;
  a8to12 : if abits > 7 generate
    agen : for i in 0 to (dbits+xbits-1)/xbits-1 generate
      u0 : axcel_ssram
      generic map (abits => abits, dbits => xbits) 
      port map ( ra => a, wa => a, di => d(xbits*(i+1)-1 downto xbits*i),
         wen => wen, width => width, wclk => clk, ren => ren, rclk => clk,
         do => q(xbits*(i+1)-1 downto xbits*i));
    end generate;
  end generate;
end;