init_dvc.c
来自「TECHWELL 之tw2835 四画面合一之驱动代码,CCIR656输出,KE」· C语言 代码 · 共 196 行
C
196 行
#include "hdr.h"
//#include "init_dvc.h"
//#include "tbl_othr_dvc.h"
//U8 reg_crsr_ctrl;
U16 reg_crsr_pos_x;
U16 reg_crsr_pos_y;
//==================================================================================
// Device init function description
//==================================================================================
void InitPg0(void)
{
U8 _t1_;
// if(BitClear(cmn_flg,CMN_JP_VDO)){
if(b_cmn_jp_vdo == VDO_NTSC){
for(_t1_=0;_t1_<4;_t1_++){
// for(_t1_=3;_t1_>=0;_t1_--){
WriteAsicTable(MASTER,DVC_PG0,0x00+0x10*_t1_,tbl_ntsc_pg0_cmn,15);
WriteAsicByte(MASTER,DVC_PG0,0x0c+0x10*_t1_,(_t1_<<6)|0x06); //... x path ANA_CH mux
WriteAsicTable(MASTER,DVC_PG0,0x80+0x10*_t1_,tbl_ntsc_pg0_scl,16);
WriteAsicByte(MASTER,DVC_PG0,0x80+0x10*_t1_,(_t1_<<6)|0x01); //... x path scale filter : quad
// WriteAsicByte(MASTER,DVC_PG0,0x80+0x10*_t1_,(_t1_<<6)|0x06); //... x path scale filter : 1/3 size
WriteAsicByte(MASTER,DVC_PG0,0x8a+0x10*_t1_,(_t1_<<6)|0x31); //... y path scale filter : quad
}
WriteAsicTable(MASTER,DVC_PG0,0x40,tbl_ntsc_pg0_sfr1,21);
WriteAsicTable(MASTER,DVC_PG0,0x60,tbl_ntsc_pg0_sfr2,21);
WriteAsicTable(MASTER,DVC_PG0,0xc0,tbl_ntsc_pg0_sfr3,11);
}
else{ //... PAL
for(_t1_=0;_t1_<4;_t1_++){
// for(_t1_=3;_t1_>=0;_t1_--){
WriteAsicTable(MASTER,DVC_PG0,0x00+0x10*_t1_,tbl_pal_pg0_cmn,15);
WriteAsicByte(MASTER,DVC_PG0,0x0c+0x10*_t1_,(_t1_<<6)|0x06); //... x path ANA_CH mux
WriteAsicTable(MASTER,DVC_PG0,0x80+0x10*_t1_,tbl_pal_pg0_scl,16);
WriteAsicByte(MASTER,DVC_PG0,0x80+0x10*_t1_,(_t1_<<6)|0x01); //... x path scale filter : quad
// WriteAsicByte(MASTER,DVC_PG0,0x80+0x10*_t1_,(_t1_<<6)|0x06); //... x path scale filter : 1/3 size
WriteAsicByte(MASTER,DVC_PG0,0x8a+0x10*_t1_,(_t1_<<6)|0x31); //... y path scale filter : quad
}
WriteAsicTable(MASTER,DVC_PG0,0x40,tbl_pal_pg0_sfr1,21);
WriteAsicTable(MASTER,DVC_PG0,0x60,tbl_pal_pg0_sfr2,21);
WriteAsicTable(MASTER,DVC_PG0,0xc0,tbl_pal_pg0_sfr3,11);
}
}
//==================================================================================
void InitPg1(void)
{
U8 _t1_;//, _t2_=0;
WriteAsicTable(MASTER,DVC_PG1,0x01,tbl_pg1_x_cmn,47);
WriteAsicTable(MASTER,DVC_PG1,0x50,tbl_pg1_y_cmn,80);
// if(BitClear(cmn_flg,CMN_JP_VDO)){
if(b_cmn_jp_vdo == VDO_NTSC){
WriteAsicTable(MASTER,DVC_PG1,0x30,tbl_ntsc_pg1_pic_qd,16); //... normal quad
// WriteAsicTable(MASTER,DVC_PG1,0x30,tbl_ntsc_pg1_pic_9_lt,16); //... non-realtime
WriteAsicTable(MASTER,DVC_PG1,0x40,tbl_ntsc_pg1_pic_9_rb,16);
WriteAsicTable(MASTER,DVC_PG1,0xa0,tbl_ntsc_pg1_enc,16);
WriteAsicByte(MASTER,DVC_PG1,0x00,0x00); //... NTSC
}
else{
WriteAsicTable(MASTER,DVC_PG1,0x30,tbl_pal_pg1_pic_qd,16); //... normal quad
// WriteAsicTable(MASTER,DVC_PG1,0x30,tbl_pal_pg1_pic_9_lt,16); //... non-realtime
WriteAsicTable(MASTER,DVC_PG1,0x40,tbl_pal_pg1_pic_9_rb,16);
WriteAsicTable(MASTER,DVC_PG1,0xa0,tbl_pal_pg1_enc,16);
WriteAsicByte(MASTER,DVC_PG1,0x00,0x80); //... PAL
}
//... queue setting
for(_t1_=0;_t1_<16;_t1_++){
//... mux queue
WriteAsicByte(MASTER,DVC_PG1,0x59,_t1_); //... queue data
WriteAsicByte(MASTER,DVC_PG1,0x5a,0x80|_t1_); //... queue addr
//... popup queue
// if(_t1_<13){
// WriteAsicByte(MASTER,DVC_PG1,0x73,(_t1_<<4)|(_t1_+1)); //... queue data
// WriteAsicByte(MASTER,DVC_PG1,0x74,((_t1_+2)<<4)|(_t1_+3)); //... queue data
// WriteAsicByte(MASTER,DVC_PG1,0x75,0x80|_t1_); //... queue addr
// }
}
WriteAsicByte(MASTER,DVC_PG1,0x73,0x01); //... queue data
WriteAsicByte(MASTER,DVC_PG1,0x74,0x23); //... queue data
WriteAsicByte(MASTER,DVC_PG1,0x75,0x80); //... queue addr
WriteAsicByte(MASTER,DVC_PG1,0x73,0x12); //... queue data
WriteAsicByte(MASTER,DVC_PG1,0x74,0x30); //... queue data
WriteAsicByte(MASTER,DVC_PG1,0x75,0x81); //... queue addr
WriteAsicByte(MASTER,DVC_PG1,0x73,0x23); //... queue data
WriteAsicByte(MASTER,DVC_PG1,0x74,0x01); //... queue data
WriteAsicByte(MASTER,DVC_PG1,0x75,0x82); //... queue addr
WriteAsicByte(MASTER,DVC_PG1,0x73,0x30); //... queue data
WriteAsicByte(MASTER,DVC_PG1,0x74,0x12); //... queue data
WriteAsicByte(MASTER,DVC_PG1,0x75,0x83); //... queue addr
WriteAsicByte(MASTER,DVC_PG1,0x56,0x40); //... start internal trigger for mux queue
}
//==================================================================================
//*
void InitPg2(void)
{
U8 _t1_;
//... OSD color index
InitOSDCol();
WriteAsicByte(MASTER,DVC_PG2,0x0f,0x0f); //... OSD Enable for Display/Capture
// WriteAsicByte(MASTER,DVC_PG2,0x0f,0x0c); //... OSD Enable for Display ---->> X
// WriteAsicByte(MASTER,DVC_PG2,0x0f,0x0a); //... OSD Enable for Display/Capture //... temporal
WriteOSDClrX(MASTER,0,0,45,31); //... max line num is 310 line for OSD
// WriteOSDClrX(MASTER,0,0,45,31); //... max line num is 310 line for OSD
// WriteOSDClrX(MASTER,0,0,45,31); //... max line num is 310 line for OSD
// WriteOSDClrX(MASTER,0,0,45,31); //... max line num is 310 line for OSD
// WriteOSDClrX(MASTER,0,0,45,31); //... max line num is 310 line for OSD
// WriteOSDClrX(MASTER,0,0,45,31); //... max line num is 310 line for OSD
// WriteOSDClrX(MASTER,0,0,45,31); //... max line num is 310 line for OSD
// WriteOSDClrX(MASTER,0,0,45,31); //... max line num is 310 line for OSD
// WriteOSDClrX(MASTER,0,0,45,31); //... max line num is 310 line for OSD
WriteOSDClrY(MASTER,0,0,45,31); //... max line num is 310 line for OSD
// WriteOSDClrY(MASTER,0,0,45,31); //... max line num is 310 line for OSD
// WriteOSDClrY(MASTER,0,0,45,31); //... max line num is 310 line for OSD
// WriteOSDClrY(MASTER,0,0,45,31); //... max line num is 310 line for OSD
// WriteOSDClrY(MASTER,0,0,45,31); //... max line num is 310 line for OSD
// WriteAsicByte(MASTER,DVC_PG2,0x10,0xb0); //... cursor
WriteAsicByte(MASTER,DVC_PG2,0x10,0xf0); //... cursor
//... other ( mouse, single box, 2d box, mask ..)
WriteAsicTable(MASTER,DVC_PG2,0x10,tbl_pg2_mse_box,80);
if(b_cmn_jp_vdo == VDO_NTSC){
WriteAsicTable(MASTER,DVC_PG2,0x60,tbl_ntsc_pg2_2dbox,32);
for(_t1_=0;_t1_<4;_t1_++) WriteAsicTable(MASTER,DVC_PG2,0x80+0x20*_t1_,tbl_ntsc_pg2_mtn,32);
}
else{
WriteAsicTable(MASTER,DVC_PG2,0x60,tbl_pal_pg2_2dbox,32);
for(_t1_=0;_t1_<4;_t1_++) WriteAsicTable(MASTER,DVC_PG2,0x80+0x20*_t1_,tbl_pal_pg2_mtn,32);
}
}
// */
//==================================================================================
//void InitReg(void)
//{
//// reg_crsr_ctrl = ReadAsicByte(MASTER,DVC_PG2,0x10);
//}
//==================================================================================
/*
void InitEncExt(void)
{
// if(BitClear(cmn_flg,CMN_JP_VDO)){
// WriteI2CTable(I2C_ID_7121_D,0x26,tbl_ntsc_saa7121_1,4);
// WriteI2CTable(I2C_ID_7121_D,0x5a,tbl_ntsc_saa7121_2,38);
// }
// else{
// WriteI2CTable(I2C_ID_7121_D,0x26,tbl_pal_saa7121_1,9);
// WriteI2CTable(I2C_ID_7121_D,0x5a,tbl_pal_saa7121_2,38);
// }
//
// WriteI2CByte(I2C_ID_7121_D,0x3a,0x13); // slave mode, CBGEN(BIT7 1:on, 0:off)
// WriteI2CByte(I2C_ID_7121_D,0x6b,0x12);
// if(b_cmn_jp_vdo == NTSC){
// WriteI2CTable(KS0123,0x00,tbl_ntsc_ks0123,17);
// }
// else{
// WriteI2CTable(KS0123,0x00,tbl_pal_ks0123,17);
// }
}
// */
//==================================================================================
/*
void InitDecPB(void)
{
if(b_jp_video == NTSC){
WriteI2CTable(TW9901,0x02,tbl_ntsc_tw9901,53);
}
else{
WriteI2CTable(TW9901,0x02,tbl_pal_tw9901,53);
}
WriteI2CByte(TW9901,0x06,0x80); // soft reset
}
//==================================================================================
// */
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