📄 wndw_vga.c
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if(b_mse_btn_dwn_rb == 1) b_mse_btn_dwn_rb = 0;
if(b_mse_clk_lb == 1){
b_mse_clk_lb = 0;
if((_osd_pos_x_ == WNDW_VGA_IE_CLOS_X)&&(_osd_pos_y_ == WNDW_VGA_IE_CLOS_Y)){
// SetBoxBtnStrPull(BOX_WNDW_QUIT);
WriteOSDClr(_pth,MASTER,WNDW_VGA_IE_POS_X,WNDW_VGA_IE_POS_Y,WNDW_VGA_IE_L,WNDW_VGA_IE_H);
WriteOSDClrX(MASTER,WNDW_VGA_IE_POS_X-1,WNDW_VGA_IE_POS_Y-1,WNDW_VGA_IE_L+2,WNDW_VGA_IE_H+2);
// DisableBox(X_PATH,BOX_WNDW_FRM-2,BOX_WNDW_FRM); // decoration wndwdow, main wndwdow
SetOSDNoMn();
// b_status_wndw = OFF;
// global_menu_crnt_pos = 30;
b_cmn_wndw_mn = OFF;
wndw_mn_pos_crnt = 30;
}
else{
if((_osd_pos_x_ == WNDW_VGA_IE_CHK_X)&&((_osd_pos_y_ == WNDW_VGA_IE_CHK_SHRP_Y)||(_osd_pos_y_ == WNDW_VGA_IE_CHK_LTI_Y)||
(_osd_pos_y_ == WNDW_VGA_IE_CHK_CTI_Y)||(_osd_pos_y_ == WNDW_VGA_IE_CHK_BW_Y))){
if(_osd_pos_y_ == WNDW_VGA_IE_CHK_SHRP_Y){
b_vga_ie_shrp ^= 1;
if(b_vga_ie_shrp) PeakFltEn();
else PeakFltDis();
}
else if(_osd_pos_y_ == WNDW_VGA_IE_CHK_LTI_Y){
b_vga_ie_lti ^= 1;
if(b_vga_ie_lti) LTIEn();
else LTIDis();
}
else if(_osd_pos_y_ == WNDW_VGA_IE_CHK_CTI_Y){
b_vga_ie_cti ^= 1;
if(b_vga_ie_cti) CTIEn();
else CTIDis();
}
else if(_osd_pos_y_ == WNDW_VGA_IE_CHK_BW_Y){
b_vga_ie_bw ^= 1;
if(b_vga_ie_bw) BwExtEn();
else BwExtDis();
}
SetWndwVGAIeOSDChk(_pth);
}
}
}
if(b_mse_clk_rb == 1) b_mse_clk_rb = 0;
if(b_mse_pshng_clk_lb == 1) b_mse_pshng_clk_lb = 0;
if(b_mse_pshng_clk_rb == 1) b_mse_pshng_clk_rb = 0;
}
//==================================================================================
//==================================================================================
//==================================================================================
U8 idata wndw_vga_nr_md = VGA_NR_TPCL;
sbit b_vga_nr_ccs = wndw_vga_flg^8;
//==================================================================================
// VGA Nr-Interlacing wndwdow function description
//==================================================================================
void SetWndwVGANrOSDRdo(U8 _pth)
{
U8 _t1_, _t2_;
for(_t1_=0;_t1_<3;_t1_++){
if(wndw_vga_nr_md == _t1_) _t2_ = OSD_RDO_CHK;
else _t2_ = OSD_RDO_BLK;
WriteOSDFnt(_pth,MASTER,WNDW_VGA_NR_RDO_X,WNDW_VGA_NR_RDO_Y+_t1_,0x00,_t2_);
}
}
//==================================================================================
void SetWndwVGANrOSDChk(U8 _pth)
{
U8 _t1_;
if(b_vga_nr_ccs == ON) _t1_ = OSD_CHK_BOX_CHK;
else _t1_ = OSD_CHK_BOX_BLK;
WriteOSDFnt(_pth,MASTER,WNDW_VGA_NR_CHK_X,WNDW_VGA_NR_CHK_Y,0x00,_t1_);
}
//==================================================================================
void CreateWndwVGANr(U8 _pth)
{
// b_status_wndw = ON;
b_cmn_wndw_mn = ON;
WriteOSDClr(_pth,MASTER,WNDW_VGA_NR_POS_X,WNDW_VGA_NR_POS_Y,WNDW_VGA_NR_L,WNDW_VGA_NR_H);
SetOSDWndw(_pth,OSD_WNDW_TYPE_MAIN,WNDW_VGA_NR_POS_X,WNDW_VGA_NR_POS_Y,WNDW_VGA_NR_L,WNDW_VGA_NR_H,str_wndw_ttl_ns_rd);
SetOSDGrp(_pth,WNDW_VGA_NR_RDO_X-1,WNDW_VGA_NR_RDO_Y,15,3,0x00,str_wndw_grp_3d_nr);
WriteOSDStr(_pth,MASTER,WNDW_VGA_NR_RDO_X+2,WNDW_VGA_NR_RDO_Y,0x00,str_wndw_vga_nr_off);
WriteOSDStr(_pth,MASTER,WNDW_VGA_NR_RDO_X+2,WNDW_VGA_NR_RDO_Y+1,0x00,str_wndw_vga_nr_tpcl);
WriteOSDStr(_pth,MASTER,WNDW_VGA_NR_RDO_X+2,WNDW_VGA_NR_RDO_Y+2,0x00,str_wndw_vga_nr_max);
WriteOSDStr(_pth,MASTER,WNDW_VGA_NR_CHK_X+2,WNDW_VGA_NR_CHK_Y,0x00,str_wndw_vga_nr_ccs);
SetWndwVGANrOSDRdo(_pth);
SetWndwVGANrOSDChk(_pth);
}
//==================================================================================
void RunWndwVGANr(U8 _pth)//U8 _osd_pos_x_, U8 _osd_pos_y_)
{
U8 _osd_pos_x_, _osd_pos_y_;
_osd_pos_x_ = GetMseOSDX(reg_crsr_pos_x);
_osd_pos_y_ = GetMseOSDY(reg_crsr_pos_y);
if(b_mse_btn_dwn_lb == 1){
b_mse_btn_dwn_lb = 0;
if((_osd_pos_x_ == WNDW_VGA_NR_CLOS_X)&&(_osd_pos_y_ == WNDW_VGA_NR_CLOS_Y)){
// SetBoxBtnStrPush(BOX_WNDW_QUIT);
}
}
if(b_mse_btn_dwn_rb == 1) b_mse_btn_dwn_rb = 0;
if(b_mse_clk_lb == 1){
b_mse_clk_lb = 0;
if((_osd_pos_x_ == WNDW_VGA_NR_CLOS_X)&&(_osd_pos_y_ == WNDW_VGA_NR_CLOS_Y)){
// SetBoxBtnStrPull(BOX_WNDW_QUIT);
WriteOSDClr(_pth,MASTER,WNDW_VGA_NR_POS_X,WNDW_VGA_NR_POS_Y,WNDW_VGA_NR_L,WNDW_VGA_NR_H);
WriteOSDClrX(MASTER,WNDW_VGA_NR_POS_X-1,WNDW_VGA_NR_POS_Y-1,WNDW_VGA_NR_L+2,WNDW_VGA_NR_H+2);
// DisableBox(X_PATH,BOX_WNDW_FRM-2,BOX_WNDW_FRM); // decoration wndwdow, main wndwdow
SetOSDNoMn();
// b_status_wndw = OFF;
// global_menu_crnt_pos = 30;
b_cmn_wndw_mn = OFF;
wndw_mn_pos_crnt = 30;
}
else{
if((_osd_pos_x_ == WNDW_VGA_NR_RDO_X)&&
((_osd_pos_y_ >= WNDW_VGA_NR_RDO_Y)&&(_osd_pos_y_ <= (WNDW_VGA_NR_RDO_Y+VGA_NR_MAX)))){
wndw_vga_nr_md = _osd_pos_y_ - WNDW_VGA_NR_RDO_Y;
if(wndw_vga_nr_md == VGA_NR_OFF) NR3DDisable();
else if(wndw_vga_nr_md == VGA_NR_TPCL) NR3DTyp();
else if(wndw_vga_nr_md == VGA_NR_MAX) NR3DMax();
SetWndwVGANrOSDRdo(_pth);
}
else{
if((_osd_pos_x_ == WNDW_VGA_NR_CHK_X)&&(_osd_pos_y_ == WNDW_VGA_NR_CHK_Y)){
b_vga_nr_ccs ^= 1;
if(b_vga_nr_ccs) CCSEn();
else CCSDis();
SetWndwVGANrOSDChk(_pth);
}
}
}
}
if(b_mse_clk_rb == 1) b_mse_clk_rb = 0;
if(b_mse_pshng_clk_lb == 1) b_mse_pshng_clk_lb = 0;
if(b_mse_pshng_clk_rb == 1) b_mse_pshng_clk_rb = 0;
}
//==================================================================================
//U8 idata cmn_vga_det;
///********************************************************************************/
///* Update : Jul 06, 2006 */
///* (new output format added : 1024x768, 1280x1024) */
///* (Note: This code is optimized for updated R,C values on circuit, */
///* therefore must be checked R,C values are updated or not. ) */
///* Last Update : Jul 20, 2006 */
///* (new output format added : 720x480P) */
///* FILE NAME : MDIN180 EDK 80C51 - MDIN180_main.c */
///* DESCRIPTION : NONE */
///********************************************************************************/
//
//#include <stdio.h>
//#include <89c51rd2.h>
//#include <string.h>
//#include <stdlib.h>
//#include <stdio.h>
//
//#include "i2c.h"
//#include "mdin180_main.h"
//#include "MDIN180_reg.h"
//
//#define MDIN180_SADDR 0xDC //MDIN-180 I2C device ID for writing
/********************************************/
/* MDIN-180 initializing and main function */
/********************************************/
void MDIN180Init(void)
{
// AVDP_RST_N = 0; // MDIN-180 HW reset
// delay(10000);
// AVDP_RST_N = 1; // MDIN-180 HW reset release
// delay(10000);
/* MDIN-180 Input Port Selection */
WriteI2CWord(I2C_ID_MDIN180, MDIN180_DISPLAY_MODE, 0x0028); // selecting input A port
//WriteI2CWord(I2C_ID_MDIN180, MDIN180_DISPLAY_MODE, 0x0020); // selecting input B port
WriteI2CWord(I2C_ID_MDIN180, MDIN180_LOCAL_REG_UPDATE, 0x0001); // local reg. update
/* MDIN180 memory configuration */
WriteI2CWord(I2C_ID_MDIN180, MDIN180_MEM_CONFIG, 0x000F); // 8MB SDRAM, 32-bit mode, 10 bit enable
//WriteI2CWord(I2C_ID_MDIN180, MDIN180_MEM_CONFIG, 0x0000); // 16MB SDRAM, 64-bit mode
WriteI2CWord(I2C_ID_MDIN180, MDIN180_LOCAL_REG_UPDATE, 0x0001); // local reg. update
/* MDIN-180 Vclk PLL setting */
MDIN180VPLLMPLLCtrl();
/* MDIN-180 Input Setting */
MDIN180InputCtrl();
/* MDIN-180 Output Sync Setting */
MDIN180SyncSize();
/* MDIN-180 Deinterlacing Parameters Setting */
MDIN180DeintRegSet();
/* MDIN-180 peaking filter enable */
MDIN180PeakFltSDEn();
/* MDIN-180 surface filter enable */
MDIN180SurfaceFltEn();
/* MDIN-180 CTI enable */
MDIN180CTIEn();
/* MDIN-180 OutputSync Reset */
MDIN180SyncReset();
MDIN180OutputCtrl();
//... set to recommendation
b_vga_or = VGA_OR_640x480;
wndw_vga_di_md = VGA_DI_ADPT;
b_vga_di_edg = ON;
b_vga_di_fst = ON;
b_vga_di_mtn = ON;
DeintAdaptStillEn();
DeintEdgeAll();
DeintFastEn();
DeintBorderEn();
b_vga_ie_shrp = OFF;
b_vga_ie_lti = OFF;
b_vga_ie_cti = OFF;
b_vga_ie_bw = OFF;
PeakFltDis();
LTIDis();
CTIDis();
BwExtDis();
wndw_vga_nr_md = VGA_NR_TPCL;
b_vga_nr_ccs = ON;
NR3DTyp();
CCSEn();
}
/********************************************/
/* MDIN-180 Video outclk PLL ctrl function */
/********************************************/
void MDIN180VPLLMPLLCtrl()
{
U16 _dly_;
WriteI2CWord(I2C_ID_MDIN180, MDIN180_PLL_DIS, 0x0003); /* PLL disable for stabilizing PLL ctrl */
WriteI2CWord(I2C_ID_MDIN180, MDIN180_OUT_SYNC_CTRL, 0x0201); /* Screen output OFF */
WriteI2CWord(I2C_ID_MDIN180,MDIN180_LOCAL_REG_UPDATE, 0x0001); /* local reg. update */
/* MDIN-180 Memory clk setting for 125MHz */
WriteI2CWord(I2C_ID_MDIN180, MDIN180_PRE_DIV_MCLK, 0x0019);
WriteI2CWord(I2C_ID_MDIN180, MDIN180_POST_DIV_MCLK, 0x0075);
WriteI2CWord(I2C_ID_MDIN180, MDIN180_POST_SCALE_MCLK, 0x0000);
// changed by hulee on jul06 2006
WriteI2CWord(I2C_ID_MDIN180, MDIN180_PLL_SEL_VCLK, 0x0001); /* Selecting XTAL_IN as input video clk */
// WriteI2CWord(I2C_ID_MDIN180, MDIN180_PLL_SEL_VCLK, 0x0000); /* Selecting CLK_A or CLK_B as input video clk */
WriteI2CWord(I2C_ID_MDIN180, MDIN180_CLK_A_DIV, 0x0000); /* VCLK_IN is clk_a = 27MHz */
// changed by hulee on jul06 2006 (inverting vclk_out for ROHM DAC)
// if ROHM DAC is used, this register value should be changed as below. (0x0004)
// if other DAC is used, adjust this register value.
WriteI2CWord(I2C_ID_MDIN180, MDIN180_VCLK_OUT_DLY_SEL, 0x0004); /* VCLK_OUT : 0ns delayed and inverted */
// WriteI2CWord(I2C_ID_MDIN180, MDIN180_VCLK_OUT_DLY_SEL, 0x0000); /* VCLK_OUT : 0ns delayed (default value) */
/* When VGA output */
// if (OutputResol == OUT_640x480) {
if(b_vga_or == VGA_OR_640x480){
WriteI2CWord(I2C_ID_MDIN180, MDIN180_POST_DIV_VCLK, 0x004A); /* changed by hulee jul06 2006 */
WriteI2CWord(I2C_ID_MDIN180, MDIN180_PRE_DIV_VCLK, 0x0009); /* changed by hulee jul06 2006 */
WriteI2CWord(I2C_ID_MDIN180, MDIN180_POST_SCALE_VCLK, 0x0003); /* changed by hulee jul06 2006 */
// WriteI2CWord(I2C_ID_MDIN180, MDIN180_POST_DIV_VCLK, 0x003D); /* modified by PNS 060308 */
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