wndw_vga.h

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//==================================================================================
//				VGA Output Resolution window definition & variable description
//==================================================================================
#define	WNDW_VGA_OR_POS_X			14//12//
#define	WNDW_VGA_OR_POS_Y			9//8//
#define	WNDW_VGA_OR_L				17//20//
#define	WNDW_VGA_OR_H				6//8//
#define	WNDW_VGA_OR_CLOS_X		(WNDW_VGA_OR_POS_X+WNDW_VGA_OR_L-1)
#define	WNDW_VGA_OR_CLOS_Y		(WNDW_VGA_OR_POS_Y)

#define	WNDW_VGA_OR_RDO_X			(WNDW_VGA_OR_POS_X+1)
#define	WNDW_VGA_OR_RDO_Y			(WNDW_VGA_OR_POS_Y+2)


#define	VGA_OR_640x480					0
#define	VGA_OR_800x600					1


//==================================================================================
extern U16 bdata	wndw_vga_flg;
extern bit	b_vga_or;


//==================================================================================
//				VGA Output Resolution wndwdow function description
//==================================================================================
extern void	SetWndwVGAOrOSD(U8 _pth);
extern void	CreateWndwVGAOr(U8 _pth);
extern void	RunWndwVGAOr(U8 _pth);








//==================================================================================
//				VGA De-Interlacing window definition & variable description
//==================================================================================
#define	WNDW_VGA_DI_POS_X			13//9//
#define	WNDW_VGA_DI_POS_Y			7//5//
#define	WNDW_VGA_DI_L				19//27//
#define	WNDW_VGA_DI_H				10//14//
#define	WNDW_VGA_DI_CLOS_X		(WNDW_VGA_DI_POS_X+WNDW_VGA_DI_L-1)
#define	WNDW_VGA_DI_CLOS_Y		(WNDW_VGA_DI_POS_Y)

#define	WNDW_VGA_DI_RDO_X			(WNDW_VGA_DI_POS_X+2)
#define	WNDW_VGA_DI_RDO_Y			(WNDW_VGA_DI_POS_Y+3)
#define	WNDW_VGA_DI_CHK_X			(WNDW_VGA_DI_POS_X+1)
//#define	WNDW_VGA_DI_CHK_EDG_X	(WNDW_VGA_DI_POS_X+1)
#define	WNDW_VGA_DI_CHK_EDG_Y	(WNDW_VGA_DI_RDO_Y+4)
//#define	WNDW_VGA_DI_CHK_FST_X	(WNDW_VGA_DI_CHK_EDG_X)
#define	WNDW_VGA_DI_CHK_FST_Y	(WNDW_VGA_DI_CHK_EDG_Y+1)
//#define	WNDW_VGA_DI_CHK_MTN_X	(WNDW_VGA_DI_CHK_EDG_X)
#define	WNDW_VGA_DI_CHK_MTN_Y	(WNDW_VGA_DI_CHK_FST_Y+1)


#define	VGA_DI_ADPT					0
#define	VGA_DI_BOB					1
#define	VGA_DI_WV					2


//==================================================================================
extern U8 idata	wndw_vga_di_md;

extern bit	b_vga_di_edg;
extern bit	b_vga_di_fst;
extern bit	b_vga_di_mtn;


//==================================================================================
//				VGA De-Interlacing wndwdow function description
//==================================================================================
extern void	SetWndwVGADiOSDRdo(U8 _pth);
extern void	SetWndwVGADiOSDChk(U8 _pth);
extern void	CreateWndwVGADi(U8 _pth);
extern void	RunWndwVGADi(U8 _pth);








//==================================================================================
//				VGA Image Enhance window definition & variable description
//==================================================================================
#define	WNDW_VGA_IE_POS_X			14//10//
#define	WNDW_VGA_IE_POS_Y			9//7//
#define	WNDW_VGA_IE_L				17//25//
#define	WNDW_VGA_IE_H				6//10//
#define	WNDW_VGA_IE_CLOS_X		(WNDW_VGA_IE_POS_X+WNDW_VGA_IE_L-1)
#define	WNDW_VGA_IE_CLOS_Y		(WNDW_VGA_IE_POS_Y)

#define	WNDW_VGA_IE_CHK_X			(WNDW_VGA_IE_POS_X+1)
//#define	WNDW_VGA_IE_CHK_SHRP_X	(WNDW_VGA_IE_POS_X+2)
#define	WNDW_VGA_IE_CHK_SHRP_Y	(WNDW_VGA_IE_POS_Y+2)
//#define	WNDW_VGA_IE_CHK_LTI_X	(WNDW_VGA_IE_CHK_SHRP_X)
#define	WNDW_VGA_IE_CHK_LTI_Y	(WNDW_VGA_IE_CHK_SHRP_Y+1)
//#define	WNDW_VGA_IE_CHK_CTI_X	(WNDW_VGA_IE_CHK_SHRP_X)
#define	WNDW_VGA_IE_CHK_CTI_Y	(WNDW_VGA_IE_CHK_LTI_Y+1)
//#define	WNDW_VGA_IE_CHK_BW_X		(WNDW_VGA_IE_CHK_SHRP_X)
#define	WNDW_VGA_IE_CHK_BW_Y		(WNDW_VGA_IE_CHK_CTI_Y+1)


//==================================================================================
extern bit	b_vga_ie_shrp;
extern bit	b_vga_ie_lti;
extern bit	b_vga_ie_cti;
extern bit	b_vga_ie_bw;


//==================================================================================
//				VGA Image Enhance wndwdow function description
//==================================================================================
extern void	SetWndwVGAIeOSDChk(U8 _pth);
extern void	CreateWndwVGAIe(U8 _pth);
extern void	RunWndwVGAIe(U8 _pth);








//==================================================================================
//				VGA Noise Reduction window definition & variable description
//==================================================================================
#define	WNDW_VGA_NR_POS_X			14
#define	WNDW_VGA_NR_POS_Y			6 
#define	WNDW_VGA_NR_L				17
#define	WNDW_VGA_NR_H				8
#define	WNDW_VGA_NR_CLOS_X		(WNDW_VGA_NR_POS_X+WNDW_VGA_NR_L-1)
#define	WNDW_VGA_NR_CLOS_Y		(WNDW_VGA_NR_POS_Y)

#define	WNDW_VGA_NR_RDO_X			(WNDW_VGA_NR_POS_X+2)
#define	WNDW_VGA_NR_RDO_Y			(WNDW_VGA_NR_POS_Y+3)
#define	WNDW_VGA_NR_CHK_X			(WNDW_VGA_NR_POS_X+1)
#define	WNDW_VGA_NR_CHK_Y			(WNDW_VGA_NR_RDO_Y+4)


#define	VGA_NR_OFF					0
#define	VGA_NR_TPCL					1
#define	VGA_NR_MAX					2


//==================================================================================
extern U8 idata	wndw_vga_nr_md;

extern bit	b_vga_nr_ccs;


//==================================================================================
//				VGA Noise Reduction wndwdow function description
//==================================================================================
extern void	SetWndwVGANrOSDRdo(U8 _pth);
extern void	SetWndwVGANrOSDChk(U8 _pth);
extern void	CreateWndwVGANr(U8 _pth);
extern void	RunWndwVGANr(U8 _pth);







//extern U8 idata	cmn_vga_det;

/********************************************************************************/
/*	FILE NAME	: MDIN180 EDK 80C51 - MDIN180_REG.H			*/
/*	DESCRIPTION	: Registers list of MDIN-180				*/
/********************************************************************************/

//#ifndef __MDIN180_REG_H__
//#define __MDIN180_REG_H__		1


/* HOST IF CONTROL REGISTERS */
#define	MDIN180_CPU_WAIT_TIME 		0x000
#define	MDIN180_CPU_BASE_ADDR 		0x002
#define	MDIN180_IRQ_ENABLE 		0x00E
#define	MDIN180_INT_STATUS 		0x010
#define	MDIN180_ENDIAN_SWAP		0x012
#define	MDIN180_INT_DETECT_MODE		0x016

/* CLOCK CONTROL REGISTERS */
#define MDIN180_PLL_DIS 		0x020
#define MDIN180_SDRAM_CLK_DLY_SEL	0x022
#define MDIN180_VCLK_OUT_DLY_SEL	0x024
#define MDIN180_DAC_DLY_SEL		0x028	
#define MDIN180_PLL_SEL_VCLK		0x02A
#define MDIN180_PRE_DIV_VCLK		0x02C	
#define MDIN180_POST_DIV_VCLK		0x02E
#define MDIN180_POST_SCALE_VCLK		0x030
#define MDIN180_PRE_DIV_MCLK		0x032
#define MDIN180_POST_DIV_MCLK		0x034
#define MDIN180_POST_SCALE_MCLK		0x036
#define MDIN180_VCLK_SEL		0x03A
#define MDIN180_MCLK_SEL		0x03C
#define MDIN180_CLK_A_DIV		0x03E
#define MDIN180_CLK_B_DIV		0x040
#define MDIN180_DAC_CLK_OUT_SEL		0x042
#define MDIN180_CLK_A_DLY_SEL		0x044
#define MDIN180_CLK_B_DLY_SEL		0x046

/* GRAPHIC ACCELERATION CONTROL REGISTERS */
#define MDIN180_GA_PROCESS_EN_DATA	0x04A
#define MDIN180_GA_SPRITE_START_RB	0x04C
#define MDIN180_GA_SPRITE_X_SIZE	0x04E
#define MDIN180_GA_WINDOW_X_POSITION	0x050
#define MDIN180_GA_WINDOW_Y_POSITION	0x052
#define MDIN180_GA_WINDOW_X_SIZE	0x054
#define MDIN180_GA_WINDOW_Y_SIZE	0x056

/* INPUT FORMAT CONTROL REGISTERS */
#define MDIN180_IN_FORMAT_CTRL		0x400
#define MDIN180_IN_FID_CTRL		0x401
#define MDIN180_IN_SYNC_CTRL		0x402
#define MDIN180_IN_ACT_OFFSET_A		0x404
#define MDIN180_IN_ACT_OFFSET_B		0x405
#define MDIN180_IN_SIZE_H_A		0x406
#define MDIN180_IN_SIZE_V_A		0x407
#define MDIN180_IN_SIZE_H_B		0x408
#define MDIN180_IN_SIZE_V_B		0x409

/* INPUT CSC CONTROL REGISTERS */
#define MDIN180_CSC_F_COEF0		0x40A
#define MDIN180_CSC_F_COEF1		0x40B
#define MDIN180_CSC_F_COEF2		0x40C
#define MDIN180_CSC_F_COEF3		0x40D
#define MDIN180_CSC_F_COEF4		0x40E
#define MDIN180_CSC_F_COEF5		0x40F
#define MDIN180_CSC_F_COEF6		0x410
#define MDIN180_CSC_F_COEF7		0x411
#define MDIN180_CSC_F_COEF8		0x412
#define MDIN180_CSC_F_OFFSET_G		0x413
#define MDIN180_CSC_F_OFFSET_B		0x414
#define MDIN180_CSC_F_OFFSET_R		0x415
#define MDIN180_CSC_F_OFFSET_Y		0x416
#define MDIN180_CSC_F_OFFSET_CB		0x417
#define MDIN180_CSC_F_OFFSET_CR		0x418
#define MDIN180_CSC_F_CTRL		0x419

/* CLAMP REGISTERS */
#define MDIN180_CLAMP_START		0x41A
#define MDIN180_CLAMP_END		0x41B

/* INPUT SYNC FORCING REGISTERS */
#define MDIN180_VSYNC_FORCED_RISING_A	0x420
#define MDIN180_VSYNC_FORCED_RISING_B	0x421

/* FRONT NOISE REDUCTION FILTER REGISTERS */
#define MDIN180_NR_FLT0			0x422
#define MDIN180_NR_FLT1			0x423
#define MDIN180_NR_FLT2			0x424
#define MDIN180_NR_FLT3			0x425
#define MDIN180_NR_FLT4			0x426
#define MDIN180_NR_FLT5			0x427
#define MDIN180_NR_FLT6			0x428
#define MDIN180_NR_FLT7			0x429
#define MDIN180_NR_FLT_ON		0x42A
#define MDIN180_NR_FLT_DIFF		0x42B
#define MDIN180_MEDIAN_FLT_ON		0x42C
#define MDIN180_MEDIAN_FLT_DIFF		0x42D
#define MDIN180_NR_FLT_DIFF_SEL		0x42E

/* SOURCE SIZE/POSITION REGISTERS */
#define MDIN180_SRC_SIZE_H		0x432
#define MDIN180_SRC_SIZE_V		0x433
#define MDIN180_SRC_POSI_H		0x434
#define MDIN180_SRC_POSI_V		0x435

/* DESTINATION SIZE/POSITION REGISTERS */