spl162001.h

GPL162001的UART模組demo程式

typedef union   // LVR_Ctrl register definition
{
	UInt16	W;
	struct
	{
		UInt16	Reserve1		: 1;
		UInt16	LVROFF			: 1;
		UInt16	Reserve2		:14;
	} B;
} P_LVR_Ctrl_DEF;

typedef union   // Watchdog_Ctrl register definition
{
	UInt16	W;
	struct
	{
		UInt16	WDGPD			: 3;
		UInt16	Reserve1		:11;
		UInt16	WDGS			: 1;
		UInt16	WDGEN			: 1;
	} B;
} P_Watchdog_Ctrl_DEF;

typedef union   // Watchdog_Clear register definition
{
	UInt16	W;
	struct
	{
		UInt16	WDGC			: 16;
	} B;
} P_Watchdog_Clear_DEF;

typedef union   // WAIT register definition
{
	UInt16	W;
	struct
	{
		UInt16	HALT			: 16;
	} B;
} P_WAIT_DEF;

typedef union   // HALT register definition
{
	UInt16	W;
	struct
	{
		UInt16	HALT			: 16;
	} B;
} P_HALT_DEF;

typedef union   // Power_State register definition
{
	UInt16	W;
	struct
	{
		UInt16	State			: 3;
		UInt16	Reserve1		:13;
	} B;
} P_Power_State_DEF;
#define BodyID_Reg				((volatile P_BodyID_DEF *)(P_BodyID))
#define CLK_Ctrl0_Reg			((volatile P_CLK_Ctrl0_DEF *)(P_CLK_Ctrl0))
#define CLK_Ctrl1_Reg			((volatile P_CLK_Ctrl1_DEF *)(P_CLK_Ctrl1))
#define Reset_Flag_Reg			((volatile P_Reset_Flag_DEF *)(P_Reset_Flag))
#define Clock_Ctrl_Reg			((volatile P_Clock_Ctrl_DEF *)(P_Clock_Ctrl))
#define LVR_Ctrl_Reg			((volatile P_LVR_Ctrl_DEF *)(P_LVR_Ctrl))
#define Watchdog_Ctrl_Reg		((volatile P_Watchdog_Ctrl_DEF *)(P_Watchdog_Ctrl))
#define Watchdog_Clear_Reg		((volatile P_Watchdog_Clear_DEF *)(P_Watchdog_Clear))
#define WAIT_Reg				((volatile P_WAIT_DEF *)(P_WAIT))
#define HALT_Reg				((volatile P_HALT_DEF *)(P_HALT))
#define Power_State_Reg			((volatile P_Power_State_DEF *)(P_Power_State))

/*****************************************************************************/
/* I/O ports registers	           			 								 */
/*****************************************************************************/
typedef union   // IOA, IOC registers definition
{
	UInt16	W;
	struct
	{
		UInt16	bit0		: 1;
		UInt16	bit1		: 1;
		UInt16	bit2		: 1;
		UInt16	bit3		: 1;
		UInt16	bit4		: 1;
		UInt16	bit5		: 1;
		UInt16	bit6		: 1;
		UInt16	bit7		: 1;
		UInt16	bit8		: 1;
		UInt16	bit9		: 1;
		UInt16	bit10		: 1;
		UInt16	bit11		: 1;
		UInt16	bit12		: 1;
		UInt16	bit13		: 1;
		UInt16	bit14		: 1;
		UInt16	bit15		: 1;
	} B;
} GEN_REG_DEF;

typedef union   // IOB registers definition
{
	UInt16	W;
	struct
	{
		UInt16	bit0		: 1;
		UInt16	bit1		: 1;
		UInt16	bit2		: 1;
		UInt16	bit3		: 1;
		UInt16	bit4		: 1;
		UInt16	bit5		: 1;
		UInt16	bit6		: 1;
		UInt16	bit7		: 1;
		UInt16	bit8		: 1;
		UInt16	bit9		: 1;
		UInt16	bit10		: 1;
		UInt16	bit11		: 1;
		UInt16	Reserve1	: 4;
	} B;	
} P_IOB_DEF;

typedef union   // IOD, IOE registers definition
{
	UInt16	W;
	struct
	{
		UInt16	bit0		: 1;
		UInt16	bit1		: 1;
		UInt16	bit2		: 1;
		UInt16	bit3		: 1;
		UInt16	bit4		: 1;
		UInt16	bit5		: 1;
		UInt16	bit6		: 1;
		UInt16	bit7		: 1;
		UInt16	bit8		: 1;
		UInt16	bit9		: 1;
		UInt16	bit10		: 1;
		UInt16	bit11		: 1;
		UInt16	bit12		: 1;
		UInt16	Reserve1	: 3;
	} B;	
} GEN1_REG_DEF;
#define IOA_Data_Reg			((volatile GEN_REG_DEF *)(P_IOA_Data))
#define IOA_Buffer_Reg			((volatile GEN_REG_DEF *)(P_IOA_Buffer))
#define IOA_Dir_Reg				((volatile GEN_REG_DEF *)(P_IOA_Dir))
#define IOA_Attrib_Reg			((volatile GEN_REG_DEF *)(P_IOA_Attrib))
#define IOA_Latch_Reg			((volatile GEN_REG_DEF *)(P_IOA_Latch))
#define IOB_Data_Reg			((volatile P_IOB_DEF *)(P_IOB_Data))
#define IOB_Buffer_Reg			((volatile P_IOB_DEF *)(P_IOB_Buffer))
#define IOB_Dir_Reg				((volatile P_IOB_DEF *)(P_IOB_Dir))
#define IOB_Attrib_Reg			((volatile P_IOB_DEF *)(P_IOB_Attrib))
#define IOB_Latch_Reg			((volatile P_IOB_DEF *)(P_IOB_Latch))
#define IOC_Data_Reg			((volatile GEN_REG_DEF *)(P_IOC_Data))
#define IOC_Buffer_Reg			((volatile GEN_REG_DEF *)(P_IOC_Buffer))
#define IOC_Dir_Reg				((volatile GEN_REG_DEF *)(P_IOC_Dir))
#define IOC_Attrib_Reg			((volatile GEN_REG_DEF *)(P_IOC_Attrib))
#define IOC_Latch_Reg			((volatile GEN_REG_DEF *)(P_IOC_Latch))
#define IOD_Data_Reg			((volatile GEN1_REG_DEF *)(P_IOD_Data))
#define IOD_Buffer_Reg			((volatile GEN1_REG_DEF *)(P_IOD_Buffer))
#define IOD_Dir_Reg				((volatile GEN1_REG_DEF *)(P_IOD_Dir))
#define IOD_Attrib_Reg			((volatile GEN1_REG_DEF *)(P_IOD_Attrib))
#define IOD_Latch_Reg			((volatile GEN1_REG_DEF *)(P_IOD_Latch))
#define IOE_Data_Reg			((volatile GEN1_REG_DEF *)(P_IOE_Data))
#define IOE_Buffer_Reg			((volatile GEN1_REG_DEF *)(P_IOE_Buffer))
#define IOE_Dir_Reg				((volatile GEN1_REG_DEF *)(P_IOE_Dir))
#define IOE_Attrib_Reg			((volatile GEN1_REG_DEF *)(P_IOE_Attrib))
#define IOE_Latch_Reg			((volatile GEN1_REG_DEF *)(P_IOE_Latch))

/*****************************************************************************/
/* Timer/Counter registers	           			 							 */
/*****************************************************************************/
typedef union   // TimerX_Ctrl registers definition (X=A,B,C,D,E,F)
{
	UInt16	W;
	struct
	{
		UInt16	SRCASEL		: 4;
		UInt16	SRCBSEL		: 3;
		UInt16	Reserve1	: 1;
		UInt16	EXTBSEL		: 2;
		UInt16	EXTASEL		: 2;
		UInt16	Reserve2	: 1;
		UInt16	TMXEN		: 1;
		UInt16	TMXIE		: 1;
		UInt16	TMXIF_C		: 1;
	} B;
} P_TimerX_Ctrl_DEF;

typedef union   // TimerX_CCP_Ctrl registers definition (X=A,B)
{
	UInt16	W;
	struct
	{
		UInt16	PWMXSEL		: 2;
		UInt16	Reserve1	: 2;
		UInt16	CMPXSEL		: 2;
		UInt16	Reserve2	: 2;
		UInt16	CAPXSEL		: 2;
		UInt16	Reserve3	: 4;
		UInt16	CCPXEN		: 2;
	} B;
} P_TimerX_CCP_Ctrl_DEF;

typedef union   // TimerX_Preload registers definition (X=A,B,C,D,E,F)
{
	UInt16	W;
	struct
	{
		UInt16	TMXPLR		:16;
	} B;
} P_TimerX_Preload_DEF;

typedef union   // TimerX_CCP registers definition (X=A,B)
{
	UInt16	W;
	struct
	{
		UInt16	TMXCCPR		:16;
	} B;
} P_TimerX_CCP_DEF;

typedef union   // TimerX_UpCount registers definition (X=A,B,C,D,E,F)
{
	UInt16	W;
	struct
	{
		UInt16	TMXUCR		:16;
	} B;
} P_TimerX_UpCount_DEF;

#define TimerA_Ctrl_Reg			  ((volatile P_TimerX_Ctrl_DEF *)(P_TimerA_Ctrl))
#define	TimerA_CCP_Ctrl_Reg       ((volatile P_TimerX_CCP_Ctrl_DEF *)(P_TimerA_CCP_Ctrl))
#define	TimerA_Preload_Reg        ((volatile P_TimerX_Preload_DEF *)(P_TimerA_Preload))
#define	TimerA_CCP_Reg            ((volatile P_TimerX_CCP_DEF *)(P_TimerA_CCP))
#define	TimerA_UpCount_Reg    	  ((volatile P_TimerX_UpCount_DEF *)(P_TimerA_UpCount))
#define TimerB_Ctrl_Reg			  ((volatile P_TimerX_Ctrl_DEF *)(P_TimerB_Ctrl))
#define	TimerB_CCP_Ctrl_Reg       ((volatile P_TimerX_CCP_Ctrl_DEF *)(P_TimerB_CCP_Ctrl))
#define	TimerB_Preload_Reg        ((volatile P_TimerX_Preload_DEF *)(P_TimerB_Preload))
#define	TimerB_CCP_Reg            ((volatile P_TimerX_CCP_DEF *)(P_TimerB_CCP))
#define	TimerB_UpCount_Reg 	      ((volatile P_TimerX_UpCount_DEF *)(P_TimerB_UpCount))
#define TimerC_Ctrl_Reg			  ((volatile P_TimerX_Ctrl_DEF *)(P_TimerC_Ctrl))
#define	TimerC_Preload_Reg        ((volatile P_TimerX_Preload_DEF *)(P_TimerC_Preload))
#define	TimerC_UpCount_Reg 	      ((volatile P_TimerX_UpCount_DEF *)(P_TimerC_UpCount))
#define TimerD_Ctrl_Reg			  ((volatile P_TimerX_Ctrl_DEF *)(P_TimerD_Ctrl))
#define	TimerD_Preload_Reg        ((volatile P_TimerX_Preload_DEF *)(P_TimerD_Preload))
#define	TimerD_UpCount_Reg	      ((volatile P_TimerX_UpCount_DEF *)(P_TimerD_UpCount))
#define TimerE_Ctrl_Reg			  ((volatile P_TimerX_Ctrl_DEF *)(P_TimerE_Ctrl))
#define	TimerE_Preload_Reg        ((volatile P_TimerX_Preload_DEF *)(P_TimerE_Preload))
#define	TimerE_UpCount_Reg 	      ((volatile P_TimerX_UpCount_DEF *)(P_TimerE_UpCount))
#define TimerF_Ctrl_Reg			  ((volatile P_TimerX_Ctrl_DEF *)(P_TimerF_Ctrl))
#define	TimerF_Preload_Reg        ((volatile P_TimerX_Preload_DEF *)(P_TimerF_Preload))
#define	TimerF_UpCount_Reg 	      ((volatile P_TimerX_UpCount_DEF *)(P_TimerF_UpCount))

/*****************************************************************************/
/* Analog input (touch panel / voice recorder) registers	           		 */
/*****************************************************************************/
typedef union   // ADC_Setup register
{
	UInt16	W;
	struct
	{
		UInt16	ASTMS		: 2;
		UInt16	ASMEN		: 1;
		UInt16	Reserve1	: 1;
		UInt16	ASSEL		: 2;
		UInt16	MICEN		: 1;
		UInt16	ASEN		: 1;
		UInt16	CLKSEL		: 2;
		UInt16	Reserve2	: 3;
		UInt16	AGCEN		: 1;
		UInt16	ADCEN		: 1;
		UInt16	ADBEN		: 1;
	} B;
} P_ADC_Setup_DEF;

typedef union   // MADC_Ctrl register
{
	UInt16	W;
	struct
	{
		UInt16	CHSEL		: 3;
		UInt16	Reserve1	: 1;
		UInt16	ASIME   	: 1;
		UInt16	MIASE		: 1;
		UInt16	STRCNV		: 1;
		UInt16	CNVRDY		: 1;
		UInt16	Reserve2	: 6;
		UInt16	ADCRIEN		: 1;
		UInt16	ADCRIF_C	: 1;
	} B;
} P_MADC_Ctrl_DEF;

typedef union   // MADC_Data register
{
	UInt16	W;
	struct
	{
		UInt16	Reserve1	: 4;
		UInt16	MADCDATA   	:12;
	} B;
} P_MADC_Data_DEF;

typedef union   // ASADC_Ctrl register
{
	UInt16	W;
	struct
	{
		UInt16	FIFOLEV		: 4;
		UInt16	ASFIL		: 4;
		UInt16	Reserve1   	: 2;
		UInt16	OVER		: 1;
		UInt16	DMA			: 1;
		UInt16	ASFOV		: 1;
		UInt16	ASFF		: 1;
		UInt16	ASIEN		: 1;
		UInt16	ASIF_C		: 1;
	} B;
} P_ASADC_Ctrl_DEF;

typedef union   // ASADC_Data register
{
	UInt16	W;
	struct