0modelsim_work.mgf

I2C IP

P cin1 _in wire
V cin1 - - - -
P inverta _in wire
V inverta - - - -
P regcascin _in wire
V regcascin - - - -
P devclrn _in wire
V devclrn - - - -
P devpor _in wire
V devpor - - - -
P combout _out wire
V combout - - - -
P regout _out wire
V regout - - - -
P cout _out wire
V cout - - - -
P cout0 _out wire
V cout0 - - - -
P cout1 _out wire
V cout1 - - - -
X stratix_lcell
V 000048 12 541 1071732054735 stratix_asynch_io
E stratix_asynch_io VERILOG 
L VL;
U VL.VERILOG_LOGIC;
G operation_mode string = "input"
G bus_hold string = "false"
G open_drain_output string = "false"
G phase_shift_delay integer = 0
P datain _in wire
V datain - - - -
P oe _in wire
V oe - - - -
P regin _in wire
V regin - - - -
P ddioregin _in wire
V ddioregin - - - -
P padio _inout wire
V padio - - - -
P delayctrlin _in wire
V delayctrlin - - - -
P combout _out wire
V combout - - - -
P regout _out wire
V regout - - - -
P ddioregout _out wire
V ddioregout - - - -
X stratix_asynch_io
V 000050 12 435 1071732054744 stratix_io_register
E stratix_io_register VERILOG 
L VL;
U VL.VERILOG_LOGIC;
G async_reset string = "none"
G sync_reset string = "none"
G power_up string = "low"
P clk _in wire
V clk - - - -
P datain _in wire
V datain - - - -
P ena _in wire
V ena - - - -
P sreset _in wire
V sreset - - - -
P areset _in wire
V areset - - - -
P devclrn _in wire
V devclrn - - - -
P devpor _in wire
V devpor - - - -
P regout _out wire
V regout - - - -
X stratix_io_register
V 000042 12 1510 1071732054753 stratix_io
E stratix_io VERILOG 
L VL;
U VL.VERILOG_LOGIC;
G operation_mode string = "input"
G ddio_mode string = "none"
G open_drain_output string = "false"
G bus_hold string = "false"
G output_register_mode string = "none"
G output_async_reset string = "none"
G output_sync_reset string = "none"
G output_power_up string = "low"
G tie_off_output_clock_enable string = "false"
G oe_register_mode string = "none"
G oe_async_reset string = "none"
G oe_sync_reset string = "none"
G oe_power_up string = "low"
G tie_off_oe_clock_enable string = "false"
G input_register_mode string = "none"
G input_async_reset string = "none"
G input_sync_reset string = "none"
G input_power_up string = "low"
G extend_oe_disable string = "false"
G sim_dll_phase_shift integer = 0
G sim_dqs_input_frequency integer = 10000
G phase_shift_delay vector = sim_dll_phase_shift*sim_dqs_input_frequency/360
P datain _in wire
V datain - - - -
P ddiodatain _in wire
V ddiodatain - - - -
P oe _in wire
V oe - - - -
P outclk _in wire
V outclk - - - -
P outclkena _in wire
V outclkena - - - -
P inclk _in wire
V inclk - - - -
P inclkena _in wire
V inclkena - - - -
P areset _in wire
V areset - - - -
P sreset _in wire
V sreset - - - -
P delayctrlin _in wire
V delayctrlin - - - -
P devclrn _in wire
V devclrn - - - -
P devpor _in wire
V devpor - - - -
P devoe _in wire
V devoe - - - -
P padio _inout wire
V padio - - - -
P combout _out wire
V combout - - - -
P regout _out wire
V regout - - - -
P ddioregout _out wire
V ddioregout - - - -
X stratix_io
V 000048 12 1122 1071732054757 stratix_mac_mult
E stratix_mac_mult VERILOG 
L VL;
U VL.VERILOG_LOGIC;
G dataa_width integer = 18
G datab_width integer = 18
G dataa_clock string = "none"
G datab_clock string = "none"
G signa_clock string = "none"
G signb_clock string = "none"
G output_clock string = "none"
G dataa_clear string = "none"
G datab_clear string = "none"
G signa_clear string = "none"
G signb_clear string = "none"
G output_clear string = "none"
G signa_internally_grounded string = "false"
G signb_internally_grounded string = "false"
G lpm_hint string = "true"
G lpm_type string = "stratix_mac_mult"
P dataa _in wire[17:0]
V dataa - - - -
P datab _in wire[17:0]
V datab - - - -
P signa _in wire
V signa - - - -
P signb _in wire
V signb - - - -
P clk _in wire[3:0]
V clk - - - -
P aclr _in wire[3:0]
V aclr - - - -
P ena _in wire[3:0]
V ena - - - -
P dataout _out wire[35:0]
V dataout - - - -
P scanouta _out wire[17:0]
V scanouta - - - -
P scanoutb _out wire[17:0]
V scanoutb - - - -
P devclrn _in wire
V devclrn - - - -
P devpor _in wire
V devpor - - - -
IB
ISB select_the  integer[31:0]
ISP string_name _in reg[32:1]
ISE select_the
IE
X stratix_mac_mult
V 000051 12 349 1071732054765 stratix_mac_register
E stratix_mac_register VERILOG 
L VL;
U VL.VERILOG_LOGIC;
G data_width integer = 18
P data _in wire[71:0]
V data - - - -
P clk _in wire
V clk - - - -
P aclr _in wire
V aclr - - - -
P ena _in wire
V ena - - - -
P async _in wire
V async - - - -
P power_up _in wire
V power_up - - - -
P dataout _out wire[71:0]
V dataout - - - -
X stratix_mac_register
V 000056 12 454 1071732054770 stratix_mac_mult_internal
E stratix_mac_mult_internal VERILOG 
L VL;
U VL.VERILOG_LOGIC;
G dataa_width integer = 18
G datab_width integer = 18
G dataout_width integer = 36
P dataa _in wire[17:0]
V dataa - - - -
P datab _in wire[17:0]
V datab - - - -
P signa _in wire
V signa - - - -
P signb _in wire
V signb - - - -
P scanouta _out wire[17:0]
V scanouta - - - -
P scanoutb _out wire[17:0]
V scanoutb - - - -
P dataout _out wire[35:0]
V dataout - - - -
X stratix_mac_mult_internal
V 000047 12 1874 1071732054776 stratix_mac_out
E stratix_mac_out VERILOG 
L VL;
U VL.VERILOG_LOGIC;
G operation_mode string = "output_only"
G dataa_width integer = 36
G datab_width integer = 36
G datac_width integer = 36
G datad_width integer = 36
G dataout_width integer = 72
G addnsub0_clock string = "none"
G addnsub1_clock string = "none"
G zeroacc_clock string = "none"
G signa_clock string = "none"
G signb_clock string = "none"
G output_clock string = "none"
G addnsub0_clear string = "none"
G addnsub1_clear string = "none"
G zeroacc_clear string = "none"
G signa_clear string = "none"
G signb_clear string = "none"
G output_clear string = "none"
G addnsub0_pipeline_clock string = "none"
G addnsub1_pipeline_clock string = "none"
G zeroacc_pipeline_clock string = "none"
G signa_pipeline_clock string = "none"
G signb_pipeline_clock string = "none"
G addnsub0_pipeline_clear string = "none"
G addnsub1_pipeline_clear string = "none"
G zeroacc_pipeline_clear string = "none"
G signa_pipeline_clear string = "none"
G signb_pipeline_clear string = "none"
G overflow_programmable_invert integer = 1'b0
G data_out_programmable_invert integer = 72'b0
G lpm_hint string = "true"
G lpm_type string = "stratix_mac_out"
P dataa _in wire[35:0]
V dataa - - - -
P datab _in wire[35:0]
V datab - - - -
P datac _in wire[35:0]
V datac - - - -
P datad _in wire[35:0]
V datad - - - -
P zeroacc _in wire
V zeroacc - - - -
P addnsub0 _in wire
V addnsub0 - - - -
P addnsub1 _in wire
V addnsub1 - - - -
P signa _in wire
V signa - - - -
P signb _in wire
V signb - - - -
P clk _in wire[3:0]
V clk - - - -
P aclr _in wire[3:0]
V aclr - - - -
P ena _in wire[3:0]
V ena - - - -
P dataout _out wire[71:0]
V dataout - - - -
P accoverflow _out wire
V accoverflow - - - -
P devclrn _in wire
V devclrn - - - -
P devpor _in wire
V devpor - - - -
IB
ISB select_the  integer[31:0]
ISP string_name _in reg[32:1]
ISE select_the
IE
X stratix_mac_out
V 000056 12 1115 1071732054785 stratix_mac_out_internal
E stratix_mac_out_internal VERILOG 
L VL;
U VL.VERILOG_LOGIC;
G operation_mode string = "output_only"
G dataa_width integer = 36
G datab_width integer = 36
G datac_width integer = 36
G datad_width integer = 36
G dataout_width integer = 72
P dataa _in wire[35:0]
V dataa - - - -
P datab _in wire[35:0]
V datab - - - -
P datac _in wire[35:0]
V datac - - - -
P datad _in wire[35:0]
V datad - - - -
P signx _in wire
V signx - - - -
P signy _in wire
V signy - - - -
P addnsub0 _in wire
V addnsub0 - - - -
P addnsub1 _in wire
V addnsub1 - - - -
P zeroacc _in wire
V zeroacc - - - -
P dataout_global _in wire[71:0]
V dataout_global - - - -
P dataout _out wire[71:0]
V dataout - - - -
P accoverflow _out wire
V accoverflow - - - -
IB
ISB add_or_sub  reg[52:0]
ISP sign_a _in reg
ISP data_a _in reg[dataa_width-1:0]
ISP sign_b _in reg
ISP data_b _in reg[datab_width-1:0]
ISP operation _in reg
ISE add_or_sub
ISB add_or_sub_accum  reg[52:0]
ISP sign_a _in reg
ISP data_a _in reg[dataa_width+15:0]
ISP sign_b _in reg
ISP data_b _in reg[dataa_width-1:0]
ISP operation _in reg
ISE add_or_sub_accum
IE
X stratix_mac_out_internal
V 000051 12 617 1071732054790 stratix_ram_register
E stratix_ram_register VERILOG 
L VL;
U VL.VERILOG_LOGIC;
G data_width integer = 144
G sclr string = "true"
G preset string = "false"
P data _in wire[143:0]
V data - - - -
P clk _in wire
V clk - - - -
P aclr _in wire
V aclr - - - -
P ena _in wire
V ena - - - -
P if_clk _in wire
V if_clk - - - -
P if_aclr _in wire
V if_aclr - - - -
P if_ena _in wire
V if_ena - - - -
P devclrn _in wire
V devclrn - - - -
P devpor _in wire
V devpor - - - -
P power_up _in wire
V power_up - - - -
P dataout _out wire[143:0]
V dataout - - - -
P aclrout _out wire
V aclrout - - - -
P done _out wire
V done - - - -
X stratix_ram_register
V 000048 12 157 1071732054796 stratix_ram_clear
E stratix_ram_clear VERILOG 
L VL;
U VL.VERILOG_LOGIC;
P aclr _in wire
V aclr - - - -
P d _in wire
V d - - - -
P q _out wire
V q - - - -
X stratix_ram_clear
V 000052 12 1785 1071732054800 stratix_ram_internal
E stratix_ram_internal VERILOG 
L VL;
U VL.VERILOG_LOGIC;
G operation_mode string = "single_port"
G ram_block_type string = "M512"
G mixed_port_feed_through_mode string = "dont_care"
G port_a_data_width integer = 16
G port_b_data_width integer = 16
G port_a_address_width integer = 16
G port_b_address_width integer = 16
G port_a_byte_enable_mask_width integer = 16
G port_b_byte_enable_mask_width integer = 16
G init_file_layout string = "none"
G port_a_first_address integer = 0
G port_a_last_address integer = 4096
G port_b_first_address integer = 0
G port_b_last_address integer = 4096
G port_a_address_clear string = "none"
G port_b_address_clear string = "none"
G mem1 integer = 512'b0
G mem2 integer = 512'b0
G mem3 integer = 512'b0
G mem4 integer = 512'b0
G mem5 integer = 512'b0
G mem6 integer = 512'b0
G mem7 integer = 512'b0
G mem8 integer = 512'b0
G mem9 integer = 512'b0
P port_a_write_enable _in wire
V port_a_write_enable - - - -
P port_b_write_enable _in wire
V port_b_write_enable - - - -
P cleara _in wire
V cleara - - - -
P clearb _in wire
V clearb - - - -
P port_a_data_in _in wire[143:0]
V port_a_data_in - - - -
P port_b_data_in _in wire[143:0]
V port_b_data_in - - - -
P port_a_address _in wire[15:0]
V port_a_address - - - -
P port_b_address _in wire[15:0]
V port_b_address - - - -
P port_a_byte_ena_mask _in wire[15:0]
V port_a_byte_ena_mask - - - -
P port_b_byte_ena_mask _in wire[15:0]
V port_b_byte_ena_mask - - - -
P port_b_read_enable _in wire
V port_b_read_enable - - - -
P port_a_clock _in wire
V port_a_clock - - - -
P port_b_clock _in wire
V port_b_clock - - - -
P same_clock _in wire
V same_clock - - - -
P port_a_data_out _out wire[143:0]
V port_a_data_out - - - -
P port_b_data_out _out wire[143:0]
V port_b_data_out - - - -
X stratix_ram_internal
V 000049 12 2921 1071732054806 stratix_ram_block
E stratix_ram_block VERILOG 
L VL;
U VL.VERILOG_LOGIC;
G mem1 integer = 512'b0
G mem2 integer = 512'b0
G mem3 integer = 512'b0
G mem4 integer = 512'b0
G mem5 integer = 512'b0
G mem6 integer = 512'b0
G mem7 integer = 512'b0
G mem8 integer = 512'b0
G mem9 integer = 512'b0
G operation_mode string = "single_port"
G mixed_port_feed_through_mode string = "dont_care"
G ram_block_type string = "auto"
G logical_ram_name string = "ram_name"
G init_file string = "init_file.hex"
G init_file_layout string = "none"
G data_interleave_width_in_bits integer = 1
G data_interleave_offset_in_bits integer = 1
G port_a_logical_ram_depth integer = 0
G port_a_logical_ram_width integer = 0
G port_a_data_in_clear string = "none"
G port_a_address_clear string = "none"
G port_a_write_enable_clear string = "none"
G port_a_data_out_clock string = "none"
G port_a_data_out_clear string = "none"
G port_a_first_address integer = 0
G port_a_last_address integer = 0
G port_a_first_bit_number integer = 0
G port_a_byte_enable_clear string = "none"
G port_a_data_in_clock string = "clock0"
G port_a_address_clock string = "clock0"
G port_a_write_enable_clock string = "clock0"
G port_a_byte_enable_clock string = "clock0"
G port_b_logical_ram_depth integer = 0
G port_b_logical_ram_width integer = 0
G port_b_data_in_clock string = "none"
G port_b_data_in_clear string = "none"
G port_b_address_clock string = "none"
G port_b_address_clear string = "none"
G port_b_read_enable_write_enable_clock string = "none"
G port_b_read_enable_write_enable_clear string = "none"
G port_b_data_out_clock string = "none"
G port_b_data_out_clear string = "none"
G port_b_first_address integer = 0
G port_b_last_address integer = 0
G port_b_first_bit_number integer = 0
G port_a_data_width integer = 144
G port_b_data_width integer = 144
G port_a_address_width integer = 144
G port_b_address_width integer = 144
G port_b_byte_enable_clear string = "none"
G port_b_byte_enable_clock string = "none"
G port_a_byte_enable_mask_width integer = 144
G port_b_byte_enable_mask_width integer = 144
G lpm_type string = "stratix_ram_block"
G connectivity_checking string = "off"
P portadatain _in wire[143:0]
V portadatain - - - -
P portaaddr _in wire[15:0]
V portaaddr - - - -
P portawe _in wire
V portawe - - - -
P portbdatain _in wire[143:0]
V portbdatain - - - -
P portbaddr _in wire[15:0]
V portbaddr - - - -
P portbrewe _in wire
V portbrewe - - - -
P clk0 _in wire
V clk0 - - - -
P clk1 _in wire
V clk1 - - - -
P ena0 _in wire
V ena0 - - - -
P ena1 _in wire
V ena1 - - - -
P clr0 _in wire
V clr0 - - - -
P clr1 _in wire
V clr1 - - - -
P portabyteenamasks _in wire[15:0]
V portabyteenamasks - - - -
P portbbyteenamasks _in wire[15:0]
V portbbyteenamasks - - - -
P devclrn _in wire
V devclrn - - - -
P devpor _in wire
V devpor - - - -
P portadataout _out wire[143:0]
V portadataout - - - -
P portbdataout _out wire[143:0]
V portbdataout - - - -
X stratix_ram_block
V 000064 12 354 1071732054812 stratix_lvds_tx_parallel_register
E stratix_lvds_tx_parallel_register VERILOG 
L VL;
U VL.VERILOG_LOGIC;
G channel_width integer = 4
P clk _in wire
V clk - - - -
P enable _in wire
V enable - - - -
P datain _in wire[9:0]
V datain - - - -
P dataout _out wire[9:0]
V dataout - - - -