0modelsim_work.mgf

I2C IP

G e3_time_delay integer = 0
G m_ph integer = 0
G m_time_delay integer = 0
G n_time_delay integer = 0
G extclk0_counter string = "e0"
G extclk1_counter string = "e1"
G extclk2_counter string = "e2"
G extclk3_counter string = "e3"
G clk0_counter string = "g0"
G clk1_counter string = "g1"
G clk2_counter string = "g2"
G clk3_counter string = "g3"
G clk4_counter string = "l0"
G clk5_counter string = "l1"
G enable0_counter string = "l0"
G enable1_counter string = "l0"
G charge_pump_current integer = 0
G loop_filter_r string = "1.0"
G loop_filter_c integer = 1
G pll_compensation_delay integer = 0
G simulation_type string = "timing"
G source_is_pll string = "off"
G clk0_phase_shift_num integer = 0
G clk1_phase_shift_num integer = 0
G clk2_phase_shift_num integer = 0
G skip_vco string = "off"
G EGPP_SCAN_CHAIN integer = 289
G GPP_SCAN_CHAIN integer = 193
G TRST integer = 5000
G TRSTCLK integer = 5000
P inclk _in wire[1:0]
V inclk - - - -
P fbin _in wire
V fbin - - - -
P ena _in wire
V ena - - - -
P clkswitch _in wire
V clkswitch - - - -
P areset _in wire
V areset - - - -
P pfdena _in wire
V pfdena - - - -
P clkena _in wire[5:0]
V clkena - - - -
P extclkena _in wire[3:0]
V extclkena - - - -
P scanclk _in wire
V scanclk - - - -
P scanaclr _in wire
V scanaclr - - - -
P scandata _in wire
V scandata - - - -
P clk _out wire[5:0]
V clk - - - -
P extclk _out wire[3:0]
V extclk - - - -
P clkbad _out wire[1:0]
V clkbad - - - -
P activeclock _out wire
V activeclock - - - -
P locked _out wire
V locked - - - -
P clkloss _out wire
V clkloss - - - -
P scandataout _out wire
V scandataout - - - -
P comparator _in wire
V comparator - - - -
P enable0 _out wire
V enable0 - - - -
P enable1 _out wire
V enable1 - - - -
IB
ISB abs  integer[31:0]
ISP value _in integer[31:0]
ISE abs
ISB slowest_clk  integer[31:0]
ISP L0 _in integer[31:0]
ISP L1 _in integer[31:0]
ISP G0 _in integer[31:0]
ISP G1 _in integer[31:0]
ISP G2 _in integer[31:0]
ISP G3 _in integer[31:0]
ISP E0 _in integer[31:0]
ISP E1 _in integer[31:0]
ISP E2 _in integer[31:0]
ISP E3 _in integer[31:0]
ISP scan_chain _in reg[40:1]
ISP refclk _in integer[31:0]
ISP m_mod _in reg[31:0]
ISE slowest_clk
ISB gcd  integer[31:0]
ISP X _in integer[31:0]
ISP Y _in integer[31:0]
ISE gcd
ISB lcm  integer[31:0]
ISP A1 _in integer[31:0]
ISP A2 _in integer[31:0]
ISP A3 _in integer[31:0]
ISP A4 _in integer[31:0]
ISP A5 _in integer[31:0]
ISP A6 _in integer[31:0]
ISP A7 _in integer[31:0]
ISP A8 _in integer[31:0]
ISP A9 _in integer[31:0]
ISP A10 _in integer[31:0]
ISP P _in integer[31:0]
ISE lcm
ISB output_counter_value  integer[31:0]
ISP clk_divide _in integer[31:0]
ISP clk_mult _in integer[31:0]
ISP M _in integer[31:0]
ISP N _in integer[31:0]
ISE output_counter_value
ISB counter_mode  reg[48:1]
ISP duty_cycle _in integer[31:0]
ISP output_counter_value _in integer[31:0]
ISE counter_mode
ISB counter_high  integer[31:0]
ISP output_counter_value _in integer[31:0]
ISP duty_cycle _in integer[31:0]
ISE counter_high
ISB counter_low  integer[31:0]
ISP output_counter_value _in integer[31:0]
ISP duty_cycle _in integer[31:0]
ISE counter_low
ISB mintimedelay  integer[31:0]
ISP t1 _in integer[31:0]
ISP t2 _in integer[31:0]
ISP t3 _in integer[31:0]
ISP t4 _in integer[31:0]
ISP t5 _in integer[31:0]
ISP t6 _in integer[31:0]
ISP t7 _in integer[31:0]
ISP t8 _in integer[31:0]
ISP t9 _in integer[31:0]
ISP t10 _in integer[31:0]
ISE mintimedelay
ISB maxnegabs  integer[31:0]
ISP t1 _in integer[31:0]
ISP t2 _in integer[31:0]
ISP t3 _in integer[31:0]
ISP t4 _in integer[31:0]
ISP t5 _in integer[31:0]
ISP t6 _in integer[31:0]
ISP t7 _in integer[31:0]
ISP t8 _in integer[31:0]
ISP t9 _in integer[31:0]
ISP t10 _in integer[31:0]
ISE maxnegabs
ISB ph_adjust  integer[31:0]
ISP tap_phase _in integer[31:0]
ISP ph_base _in integer[31:0]
ISE ph_adjust
ISB counter_time_delay  integer[31:0]
ISP clk_time_delay _in integer[31:0]
ISP m_time_delay _in integer[31:0]
ISP n_time_delay _in integer[31:0]
ISE counter_time_delay
ISB counter_initial  integer[31:0]
ISP tap_phase _in integer[31:0]
ISP m _in integer[31:0]
ISP n _in integer[31:0]
ISE counter_initial
ISB counter_ph  integer[31:0]
ISP tap_phase _in integer[31:0]
ISP m _in integer[31:0]
ISP n _in integer[31:0]
ISE counter_ph
ISB translate_string  reg[48:1]
ISP mode _in reg
ISE translate_string
ISB str2int  integer[31:0]
ISP s _in reg[128:1]
ISE str2int
ISB get_int_phase_shift  integer[31:0]
ISP s _in reg[128:1]
ISP i_phase_shift _in integer[31:0]
ISE get_int_phase_shift
ISB get_phase_degree  integer[31:0]
ISP phase_shift _in integer[31:0]
ISE get_phase_degree
ISB alpha_tolower  reg[144:1]
ISP given_string _in reg[144:1]
ISE alpha_tolower
IE
X stratix_pll
V 000042 12 260 1071731857888 stratix_dll
E stratix_dll VERILOG 
L VL;
U VL.VERILOG_LOGIC;
G input_frequency integer = 10000
G phase_shift integer = 0
G sim_valid_lock integer = 1
G sim_invalid_lock integer = 5
P clk _in wire
V clk - - - -
P delayctrlout _out wire
V delayctrlout - - - -
X stratix_dll
V 000043 12 617 1071731857892 stratix_jtag
E stratix_jtag VERILOG 
L VL;
U VL.VERILOG_LOGIC;
P tms _in wire
V tms - - - -
P tck _in wire
V tck - - - -
P tdi _in wire
V tdi - - - -
P ntrst _in wire
V ntrst - - - -
P tdoutap _in wire
V tdoutap - - - -
P tdouser _in wire
V tdouser - - - -
P tdo _out wire
V tdo - - - -
P tmsutap _out wire
V tmsutap - - - -
P tckutap _out wire
V tckutap - - - -
P tdiutap _out wire
V tdiutap - - - -
P shiftuser _out wire
V shiftuser - - - -
P clkdruser _out wire
V clkdruser - - - -
P updateuser _out wire
V updateuser - - - -
P runidleuser _out wire
V runidleuser - - - -
P usr1user _out wire
V usr1user - - - -
X stratix_jtag
V 000047 12 283 1071731857896 stratix_crcblock
E stratix_crcblock VERILOG 
L VL;
U VL.VERILOG_LOGIC;
G oscillator_divider integer = 1
P clk _in wire
V clk - - - -
P shiftnld _in wire
V shiftnld - - - -
P ldsrc _in wire
V ldsrc - - - -
P crcerror _out wire
V crcerror - - - -
P regout _out wire
V regout - - - -
X stratix_crcblock
V 000046 12 544 1071731857900 stratix_rublock
E stratix_rublock VERILOG 
L VL;
U VL.VERILOG_LOGIC;
G sim_init_config string = "factory"
G sim_init_watchdog_value integer = 0
G sim_init_page_select integer = 0
G sim_init_status integer = 0
G lpm_type string = "stratix_rublock"
P clk _in wire
V clk - - - -
P shiftnld _in wire
V shiftnld - - - -
P captnupdt _in wire
V captnupdt - - - -
P regin _in wire
V regin - - - -
P rsttimer _in wire
V rsttimer - - - -
P rconfig _in wire
V rconfig - - - -
P regout _out wire
V regout - - - -
P pgmout _out wire[2:0]
V pgmout - - - -
X stratix_rublock
V 000034 12 444 1071731860202 i2c
E i2c VERILOG 
L VL;
U VL.VERILOG_LOGIC;
P r_w _in wire
V r_w - - - -
P clk _in wire
V clk - - - -
P reset _in wire
V reset - - - -
P as _in wire
V as - - - -
P addr_bus _in wire[23:0]
V addr_bus - - - -
P ds _in wire
V ds - - - -
P sda _inout wire
V sda - - - -
P scl _inout wire
V scl - - - -
P data_bus _inout wire[7:0]
V data_bus - - - -
P mcf _inout wire
V mcf - - - -
P dtack _out wire
V dtack - - - -
P irq _out wire
V irq - - - -
X i2c
V 000040 12 269 1071732054652 PRIM_DFFE
E PRIM_DFFE VERILOG UDP
L VL;
U VL.VERILOG_LOGIC;
P Q _out reg
V Q - - - -
P ENA _in wire
V ENA - - - -
P D _in wire
V D - - - -
P CLK _in wire
V CLK - - - -
P CLRN _in wire
V CLRN - - - -
P PRN _in wire
V PRN - - - -
P notifier _in wire
V notifier - - - -
X PRIM_DFFE
V 000035 12 218 1071732054665 dffe
E dffe VERILOG 
L VL;
U VL.VERILOG_LOGIC;
P Q _out wire
V Q - - - -
P CLK _in wire
V CLK - - - -
P ENA _in wire
V ENA - - - -
P D _in wire
V D - - - -
P CLRN _in wire
V CLRN - - - -
P PRN _in wire
V PRN - - - -
X dffe
V 000036 12 189 1071732054672 latch
E latch VERILOG 
L VL;
U VL.VERILOG_LOGIC;
P D _in wire
V D - - - -
P ENA _in wire
V ENA - - - -
P PRE _in wire
V PRE - - - -
P CLR _in wire
V CLR - - - -
P Q _out wire
V Q - - - -
X latch
V 000036 12 154 1071732054677 mux21
E mux21 VERILOG 
L VL;
U VL.VERILOG_LOGIC;
P MO _out wire
V MO - - - -
P A _in wire
V A - - - -
P B _in wire
V B - - - -
P S _in wire
V S - - - -
X mux21
V 000035 12 104 1071732054686 and1
E and1 VERILOG 
L VL;
U VL.VERILOG_LOGIC;
P Y _out wire
V Y - - - -
P IN1 _in wire
V IN1 - - - -
X and1
V 000036 12 118 1071732054696 and16
E and16 VERILOG 
L VL;
U VL.VERILOG_LOGIC;
P Y _out wire[15:0]
V Y - - - -
P IN1 _in wire[15:0]
V IN1 - - - -
X and16
V 000037 12 174 1071732054701 bmux21
E bmux21 VERILOG 
L VL;
U VL.VERILOG_LOGIC;
P MO _out wire[15:0]
V MO - - - -
P A _in wire[15:0]
V A - - - -
P B _in wire[15:0]
V B - - - -
P S _in wire
V S - - - -
X bmux21
V 000039 12 178 1071732054705 b17mux21
E b17mux21 VERILOG 
L VL;
U VL.VERILOG_LOGIC;
P MO _out wire[16:0]
V MO - - - -
P A _in wire[16:0]
V A - - - -
P B _in wire[16:0]
V B - - - -
P S _in wire
V S - - - -
X b17mux21
V 000037 12 156 1071732054709 nmux21
E nmux21 VERILOG 
L VL;
U VL.VERILOG_LOGIC;
P MO _out wire
V MO - - - -
P A _in wire
V A - - - -
P B _in wire
V B - - - -
P S _in wire
V S - - - -
X nmux21
V 000038 12 173 1071732054715 b5mux21
E b5mux21 VERILOG 
L VL;
U VL.VERILOG_LOGIC;
P MO _out wire[4:0]
V MO - - - -
P A _in wire[4:0]
V A - - - -
P B _in wire[4:0]
V B - - - -
P S _in wire
V S - - - -
X b5mux21
V 000051 12 919 1071732054719 stratix_asynch_lcell
E stratix_asynch_lcell VERILOG 
L VL;
U VL.VERILOG_LOGIC;
G operation_mode string = "normal"
G sum_lutc_input string = "datac"
G lut_mask string = "ffff"
G cin_used string = "false"
G cin0_used string = "false"
G cin1_used string = "false"
P dataa _in wire
V dataa - - - -
P datab _in wire
V datab - - - -
P datac _in wire
V datac - - - -
P datad _in wire
V datad - - - -
P cin _in wire
V cin - - - -
P cin0 _in wire
V cin0 - - - -
P cin1 _in wire
V cin1 - - - -
P inverta _in wire
V inverta - - - -
P qfbkin _in wire
V qfbkin - - - -
P regin _out wire
V regin - - - -
P combout _out wire
V combout - - - -
P cout _out wire
V cout - - - -
P cout0 _out wire
V cout0 - - - -
P cout1 _out wire
V cout1 - - - -
IB
ISB str_to_bin  reg[16:1]
ISP s _in reg[32:1]
ISE str_to_bin
ISB lut4  reg
ISP lut_mask _in reg[32:1]
ISP dataa _in reg
ISP datab _in reg
ISP datac _in reg
ISP datad _in reg
ISE lut4
IE
X stratix_asynch_lcell
V 000053 12 650 1071732054726 stratix_lcell_register
E stratix_lcell_register VERILOG 
L VL;
U VL.VERILOG_LOGIC;
G synch_mode string = "off"
G register_cascade_mode string = "off"
G power_up string = "low"
G x_on_violation string = "on"
P clk _in wire
V clk - - - -
P aclr _in wire
V aclr - - - -
P aload _in wire
V aload - - - -
P sclr _in wire
V sclr - - - -
P sload _in wire
V sload - - - -
P ena _in wire
V ena - - - -
P datain _in wire
V datain - - - -
P datac _in wire
V datac - - - -
P regcascin _in wire
V regcascin - - - -
P devclrn _in wire
V devclrn - - - -
P devpor _in wire
V devpor - - - -
P regout _out wire
V regout - - - -
P qfbkout _out wire
V qfbkout - - - -
X stratix_lcell_register
V 000045 12 1177 1071732054731 stratix_lcell
E stratix_lcell VERILOG 
L VL;
U VL.VERILOG_LOGIC;
G operation_mode string = "normal"
G synch_mode string = "off"
G register_cascade_mode string = "off"
G sum_lutc_input string = "datac"
G lut_mask string = "ffff"
G power_up string = "low"
G cin_used string = "false"
G cin0_used string = "false"
G cin1_used string = "false"
G output_mode string = "comb_only"
G lpm_type string = "stratix_lcell"
G x_on_violation string = "on"
P clk _in wire
V clk - - - -
P dataa _in wire
V dataa - - - -
P datab _in wire
V datab - - - -
P datac _in wire
V datac - - - -
P datad _in wire
V datad - - - -
P aclr _in wire
V aclr - - - -
P aload _in wire
V aload - - - -
P sclr _in wire
V sclr - - - -
P sload _in wire
V sload - - - -
P ena _in wire
V ena - - - -
P cin _in wire
V cin - - - -
P cin0 _in wire
V cin0 - - - -