0modelsim_work.mgf

I2C IP

V 000040 12 269 1071731857729 PRIM_DFFE
E PRIM_DFFE VERILOG UDP
L VL;
U VL.VERILOG_LOGIC;
P Q _out reg
V Q - - - -
P ENA _in wire
V ENA - - - -
P D _in wire
V D - - - -
P CLK _in wire
V CLK - - - -
P CLRN _in wire
V CLRN - - - -
P PRN _in wire
V PRN - - - -
P notifier _in wire
V notifier - - - -
X PRIM_DFFE
V 000035 12 218 1071731857733 dffe
E dffe VERILOG 
L VL;
U VL.VERILOG_LOGIC;
P Q _out wire
V Q - - - -
P CLK _in wire
V CLK - - - -
P ENA _in wire
V ENA - - - -
P D _in wire
V D - - - -
P CLRN _in wire
V CLRN - - - -
P PRN _in wire
V PRN - - - -
X dffe
V 000036 12 189 1071731857739 latch
E latch VERILOG 
L VL;
U VL.VERILOG_LOGIC;
P D _in wire
V D - - - -
P ENA _in wire
V ENA - - - -
P PRE _in wire
V PRE - - - -
P CLR _in wire
V CLR - - - -
P Q _out wire
V Q - - - -
X latch
V 000036 12 154 1071731857744 mux21
E mux21 VERILOG 
L VL;
U VL.VERILOG_LOGIC;
P MO _out wire
V MO - - - -
P A _in wire
V A - - - -
P B _in wire
V B - - - -
P S _in wire
V S - - - -
X mux21
V 000035 12 104 1071731857749 and1
E and1 VERILOG 
L VL;
U VL.VERILOG_LOGIC;
P Y _out wire
V Y - - - -
P IN1 _in wire
V IN1 - - - -
X and1
V 000036 12 118 1071731857754 and16
E and16 VERILOG 
L VL;
U VL.VERILOG_LOGIC;
P Y _out wire[15:0]
V Y - - - -
P IN1 _in wire[15:0]
V IN1 - - - -
X and16
V 000037 12 174 1071731857759 bmux21
E bmux21 VERILOG 
L VL;
U VL.VERILOG_LOGIC;
P MO _out wire[15:0]
V MO - - - -
P A _in wire[15:0]
V A - - - -
P B _in wire[15:0]
V B - - - -
P S _in wire
V S - - - -
X bmux21
V 000039 12 178 1071731857763 b17mux21
E b17mux21 VERILOG 
L VL;
U VL.VERILOG_LOGIC;
P MO _out wire[16:0]
V MO - - - -
P A _in wire[16:0]
V A - - - -
P B _in wire[16:0]
V B - - - -
P S _in wire
V S - - - -
X b17mux21
V 000037 12 156 1071731857767 nmux21
E nmux21 VERILOG 
L VL;
U VL.VERILOG_LOGIC;
P MO _out wire
V MO - - - -
P A _in wire
V A - - - -
P B _in wire
V B - - - -
P S _in wire
V S - - - -
X nmux21
V 000038 12 173 1071731857771 b5mux21
E b5mux21 VERILOG 
L VL;
U VL.VERILOG_LOGIC;
P MO _out wire[4:0]
V MO - - - -
P A _in wire[4:0]
V A - - - -
P B _in wire[4:0]
V B - - - -
P S _in wire
V S - - - -
X b5mux21
V 000051 12 919 1071731857775 stratix_asynch_lcell
E stratix_asynch_lcell VERILOG 
L VL;
U VL.VERILOG_LOGIC;
G operation_mode string = "normal"
G sum_lutc_input string = "datac"
G lut_mask string = "ffff"
G cin_used string = "false"
G cin0_used string = "false"
G cin1_used string = "false"
P dataa _in wire
V dataa - - - -
P datab _in wire
V datab - - - -
P datac _in wire
V datac - - - -
P datad _in wire
V datad - - - -
P cin _in wire
V cin - - - -
P cin0 _in wire
V cin0 - - - -
P cin1 _in wire
V cin1 - - - -
P inverta _in wire
V inverta - - - -
P qfbkin _in wire
V qfbkin - - - -
P regin _out wire
V regin - - - -
P combout _out wire
V combout - - - -
P cout _out wire
V cout - - - -
P cout0 _out wire
V cout0 - - - -
P cout1 _out wire
V cout1 - - - -
IB
ISB str_to_bin  reg[16:1]
ISP s _in reg[32:1]
ISE str_to_bin
ISB lut4  reg
ISP lut_mask _in reg[32:1]
ISP dataa _in reg
ISP datab _in reg
ISP datac _in reg
ISP datad _in reg
ISE lut4
IE
X stratix_asynch_lcell
V 000053 12 650 1071731857780 stratix_lcell_register
E stratix_lcell_register VERILOG 
L VL;
U VL.VERILOG_LOGIC;
G synch_mode string = "off"
G register_cascade_mode string = "off"
G power_up string = "low"
G x_on_violation string = "on"
P clk _in wire
V clk - - - -
P aclr _in wire
V aclr - - - -
P aload _in wire
V aload - - - -
P sclr _in wire
V sclr - - - -
P sload _in wire
V sload - - - -
P ena _in wire
V ena - - - -
P datain _in wire
V datain - - - -
P datac _in wire
V datac - - - -
P regcascin _in wire
V regcascin - - - -
P devclrn _in wire
V devclrn - - - -
P devpor _in wire
V devpor - - - -
P regout _out wire
V regout - - - -
P qfbkout _out wire
V qfbkout - - - -
X stratix_lcell_register
V 000045 12 1177 1071731857785 stratix_lcell
E stratix_lcell VERILOG 
L VL;
U VL.VERILOG_LOGIC;
G operation_mode string = "normal"
G synch_mode string = "off"
G register_cascade_mode string = "off"
G sum_lutc_input string = "datac"
G lut_mask string = "ffff"
G power_up string = "low"
G cin_used string = "false"
G cin0_used string = "false"
G cin1_used string = "false"
G output_mode string = "comb_only"
G lpm_type string = "stratix_lcell"
G x_on_violation string = "on"
P clk _in wire
V clk - - - -
P dataa _in wire
V dataa - - - -
P datab _in wire
V datab - - - -
P datac _in wire
V datac - - - -
P datad _in wire
V datad - - - -
P aclr _in wire
V aclr - - - -
P aload _in wire
V aload - - - -
P sclr _in wire
V sclr - - - -
P sload _in wire
V sload - - - -
P ena _in wire
V ena - - - -
P cin _in wire
V cin - - - -
P cin0 _in wire
V cin0 - - - -
P cin1 _in wire
V cin1 - - - -
P inverta _in wire
V inverta - - - -
P regcascin _in wire
V regcascin - - - -
P devclrn _in wire
V devclrn - - - -
P devpor _in wire
V devpor - - - -
P combout _out wire
V combout - - - -
P regout _out wire
V regout - - - -
P cout _out wire
V cout - - - -
P cout0 _out wire
V cout0 - - - -
P cout1 _out wire
V cout1 - - - -
X stratix_lcell
V 000048 12 541 1071731857789 stratix_asynch_io
E stratix_asynch_io VERILOG 
L VL;
U VL.VERILOG_LOGIC;
G operation_mode string = "input"
G bus_hold string = "false"
G open_drain_output string = "false"
G phase_shift_delay integer = 0
P datain _in wire
V datain - - - -
P oe _in wire
V oe - - - -
P regin _in wire
V regin - - - -
P ddioregin _in wire
V ddioregin - - - -
P padio _inout wire
V padio - - - -
P delayctrlin _in wire
V delayctrlin - - - -
P combout _out wire
V combout - - - -
P regout _out wire
V regout - - - -
P ddioregout _out wire
V ddioregout - - - -
X stratix_asynch_io
V 000050 12 435 1071731857794 stratix_io_register
E stratix_io_register VERILOG 
L VL;
U VL.VERILOG_LOGIC;
G async_reset string = "none"
G sync_reset string = "none"
G power_up string = "low"
P clk _in wire
V clk - - - -
P datain _in wire
V datain - - - -
P ena _in wire
V ena - - - -
P sreset _in wire
V sreset - - - -
P areset _in wire
V areset - - - -
P devclrn _in wire
V devclrn - - - -
P devpor _in wire
V devpor - - - -
P regout _out wire
V regout - - - -
X stratix_io_register
V 000042 12 1510 1071731857799 stratix_io
E stratix_io VERILOG 
L VL;
U VL.VERILOG_LOGIC;
G operation_mode string = "input"
G ddio_mode string = "none"
G open_drain_output string = "false"
G bus_hold string = "false"
G output_register_mode string = "none"
G output_async_reset string = "none"
G output_sync_reset string = "none"
G output_power_up string = "low"
G tie_off_output_clock_enable string = "false"
G oe_register_mode string = "none"
G oe_async_reset string = "none"
G oe_sync_reset string = "none"
G oe_power_up string = "low"
G tie_off_oe_clock_enable string = "false"
G input_register_mode string = "none"
G input_async_reset string = "none"
G input_sync_reset string = "none"
G input_power_up string = "low"
G extend_oe_disable string = "false"
G sim_dll_phase_shift integer = 0
G sim_dqs_input_frequency integer = 10000
G phase_shift_delay vector = sim_dll_phase_shift*sim_dqs_input_frequency/360
P datain _in wire
V datain - - - -
P ddiodatain _in wire
V ddiodatain - - - -
P oe _in wire
V oe - - - -
P outclk _in wire
V outclk - - - -
P outclkena _in wire
V outclkena - - - -
P inclk _in wire
V inclk - - - -
P inclkena _in wire
V inclkena - - - -
P areset _in wire
V areset - - - -
P sreset _in wire
V sreset - - - -
P delayctrlin _in wire
V delayctrlin - - - -
P devclrn _in wire
V devclrn - - - -
P devpor _in wire
V devpor - - - -
P devoe _in wire
V devoe - - - -
P padio _inout wire
V padio - - - -
P combout _out wire
V combout - - - -
P regout _out wire
V regout - - - -
P ddioregout _out wire
V ddioregout - - - -
X stratix_io
V 000048 12 1122 1071731857803 stratix_mac_mult
E stratix_mac_mult VERILOG 
L VL;
U VL.VERILOG_LOGIC;
G dataa_width integer = 18
G datab_width integer = 18
G dataa_clock string = "none"
G datab_clock string = "none"
G signa_clock string = "none"
G signb_clock string = "none"
G output_clock string = "none"
G dataa_clear string = "none"
G datab_clear string = "none"
G signa_clear string = "none"
G signb_clear string = "none"
G output_clear string = "none"
G signa_internally_grounded string = "false"
G signb_internally_grounded string = "false"
G lpm_hint string = "true"
G lpm_type string = "stratix_mac_mult"
P dataa _in wire[17:0]
V dataa - - - -
P datab _in wire[17:0]
V datab - - - -
P signa _in wire
V signa - - - -
P signb _in wire
V signb - - - -
P clk _in wire[3:0]
V clk - - - -
P aclr _in wire[3:0]
V aclr - - - -
P ena _in wire[3:0]
V ena - - - -
P dataout _out wire[35:0]
V dataout - - - -
P scanouta _out wire[17:0]
V scanouta - - - -
P scanoutb _out wire[17:0]
V scanoutb - - - -
P devclrn _in wire
V devclrn - - - -
P devpor _in wire
V devpor - - - -
IB
ISB select_the  integer[31:0]
ISP string_name _in reg[32:1]
ISE select_the
IE
X stratix_mac_mult
V 000051 12 349 1071731857807 stratix_mac_register
E stratix_mac_register VERILOG 
L VL;
U VL.VERILOG_LOGIC;
G data_width integer = 18
P data _in wire[71:0]
V data - - - -
P clk _in wire
V clk - - - -
P aclr _in wire
V aclr - - - -
P ena _in wire
V ena - - - -
P async _in wire
V async - - - -
P power_up _in wire
V power_up - - - -
P dataout _out wire[71:0]
V dataout - - - -
X stratix_mac_register
V 000056 12 454 1071731857812 stratix_mac_mult_internal
E stratix_mac_mult_internal VERILOG 
L VL;
U VL.VERILOG_LOGIC;
G dataa_width integer = 18
G datab_width integer = 18
G dataout_width integer = 36
P dataa _in wire[17:0]
V dataa - - - -
P datab _in wire[17:0]
V datab - - - -
P signa _in wire
V signa - - - -
P signb _in wire
V signb - - - -
P scanouta _out wire[17:0]
V scanouta - - - -
P scanoutb _out wire[17:0]
V scanoutb - - - -
P dataout _out wire[35:0]
V dataout - - - -
X stratix_mac_mult_internal
V 000047 12 1874 1071731857817 stratix_mac_out
E stratix_mac_out VERILOG 
L VL;
U VL.VERILOG_LOGIC;
G operation_mode string = "output_only"
G dataa_width integer = 36
G datab_width integer = 36
G datac_width integer = 36
G datad_width integer = 36
G dataout_width integer = 72
G addnsub0_clock string = "none"
G addnsub1_clock string = "none"
G zeroacc_clock string = "none"
G signa_clock string = "none"
G signb_clock string = "none"
G output_clock string = "none"
G addnsub0_clear string = "none"
G addnsub1_clear string = "none"
G zeroacc_clear string = "none"
G signa_clear string = "none"
G signb_clear string = "none"
G output_clear string = "none"
G addnsub0_pipeline_clock string = "none"
G addnsub1_pipeline_clock string = "none"
G zeroacc_pipeline_clock string = "none"
G signa_pipeline_clock string = "none"
G signb_pipeline_clock string = "none"
G addnsub0_pipeline_clear string = "none"
G addnsub1_pipeline_clear string = "none"
G zeroacc_pipeline_clear string = "none"
G signa_pipeline_clear string = "none"
G signb_pipeline_clear string = "none"
G overflow_programmable_invert integer = 1'b0
G data_out_programmable_invert integer = 72'b0
G lpm_hint string = "true"
G lpm_type string = "stratix_mac_out"
P dataa _in wire[35:0]
V dataa - - - -
P datab _in wire[35:0]
V datab - - - -
P datac _in wire[35:0]
V datac - - - -
P datad _in wire[35:0]
V datad - - - -
P zeroacc _in wire
V zeroacc - - - -
P addnsub0 _in wire
V addnsub0 - - - -
P addnsub1 _in wire
V addnsub1 - - - -
P signa _in wire
V signa - - - -
P signb _in wire
V signb - - - -
P clk _in wire[3:0]
V clk - - - -
P aclr _in wire[3:0]
V aclr - - - -
P ena _in wire[3:0]
V ena - - - -
P dataout _out wire[71:0]
V dataout - - - -
P accoverflow _out wire
V accoverflow - - - -
P devclrn _in wire
V devclrn - - - -
P devpor _in wire
V devpor - - - -
IB
ISB select_the  integer[31:0]
ISP string_name _in reg[32:1]
ISE select_the
IE
X stratix_mac_out
V 000056 12 1115 1071731857821 stratix_mac_out_internal
E stratix_mac_out_internal VERILOG 
L VL;
U VL.VERILOG_LOGIC;
G operation_mode string = "output_only"
G dataa_width integer = 36
G datab_width integer = 36