spl162001.inc

GPL162001的I2C功能demo程式

//#define CPU24MHZ
//#define CPU6MHZ

//.define		SDPLAYEXT	2


.define		SDPLAYBLK	16

.define		USB_HOST	1
.define		USB_DEV		0

.define		FRAME_BUF_ADDR	0x4800

.define		ENTER_WAIT      0x5005
.define		ENTER_HALT      0x500A
.define		ENTER_SLEEP     0xA00A

.define		NOPIX           0x0000
.define		PIX4BITS        0x0001
.define		PIX8BITS        0x0002
.define		PIX12BITS       0x0003
.define		SKIPWBUF        0x0010
.define		LCDPIX          0x0020
.define		NORMPIX         0x0000
.define		TBOFF		0x0100
.define		SYSOFF		0x0080
.define		MEMOFF		0x0040
.define		BUSOFF		0x0020
.define		C32KOFF		0x0400
.define		DISDATAPH	0x8000
.define		DATAPH		0x4000
.define		DATAPL		0x0000

.define		LCD_EXC         0x0001
.define		LCD_REV         0x0002
.define		LCD_HINV        0x0004
.define		LCD_VINV        0x0008

.define		INT_KeyChange   0x8000
.define		INT_ADC         0x4000
.define		INT_SensorFull  0x2000
.define		INT_SensorHFull 0x1000
.define		INT_UART        0x0800
.define		INT_SPI         0x0400
.define		INT_LCDFP       0x0200
.define		INT_TouchPanel  0x0100
.define		INT_ADCFull     0x0080
.define		INT_AudioB      0x0020
.define		INT_AudioA      0x0010
.define		INT_USB         0x0008
.define		INT_DMA         0x0004
.define		INT_INT2        0x0002
.define		INT_INT1        0x0001

.define		INT_TimerD      0x8000
.define		INT_TimerC      0x4000
.define		INT_TimerB      0x2000
.define		INT_TimerA      0x1000
.define		INT_KeyScan     0x0800
.define		INT_TimeBaseC   0x0400
.define		INT_TimeBaseB   0x0200
.define		INT_TimeBaseA   0x0100
.define		INT_LVD         0x0080
.define		INT_SD          0x0040
.define		INT_I2C			0x0020
.define		INT_NAND        0x0010
.define		INT_ShutDownb   0x0008
.define		INT_SCH         0x0004
.define		INT_ALM         0x0002
.define		INT_HMS         0x0001

.define		MASK_INT1EN     0x0001
.define		MASK_INT1OFF    0xFFFE
.define		MASK_INT2EN     0x0002
.define		MASK_INT2OFF    0xFFFD
.define		MASK_SHUTDOWNEN 0x0008
.define		MASK_SHUTDOWNOFF	0xFFF7
.define		MASK_INT1RISE   0x0010
.define		MASK_INT1FALL   0x0000
.define		MASK_INT2RISE   0x0020
.define		MASK_INT2FALL   0x0000
.define		MASK_KCEN       0x8000
.define		MASK_KCOFF      0x7FFF

.define		DMA_Enable      0x0001
.define		DMA_Busy        0x0002
.define		DMA_Soft_Mode   0x0000
.define		DMA_Ext_Mode    0x0004
.define		DMA_Double_Full 0x0008
.define		DMA_Normal_Int  0x0008
.define		DMA_Dst_Incr    0x0000
.define		DMA_Dst_Decr    0x0010
.define		DMA_Src_Incr    0x0000
.define		DMA_Src_Decr    0x0020
.define		DMA_Dst_Fix     0x0040
.define		DMA_Src_Fix     0x0080
.define		DMA_Int_En      0x0100
.define		DMA_Reset       0x0200
.define		DMA_M2M         0x0000
.define		DMA_M2I         0x0400
.define		DMA_I2M         0x0800
.define		DMA_I2I         0x0C00
.define		DMA_Src_Byte    0x1000
.define		DMA_Dst_Byte    0x2000
.define		DMA_Single_Mode 0x0000
.define		DMA_Demand_Mode 0x4000
.define		DMA_Write_Req   0x8000
.define		DMA_Read_Req    0x0000

.define		DMASRC_USB	0
.define		DMASRC_AUDA     1
.define		DMASRC_UTX      2
.define		DMASRC_URX      3
.define		DMASRC_SD       4
.define		DMASRC_NAND     5
.define		DMASRC_SPB      6
.define		DMASRC_AUDB     7
.define		DMASRC_ADCF     8


//========================================================================================
//Definitions for Peripheral Control Register
//========================================================================================
IOBASE:           .VDEF      0x7000

SYSBASE:          .VDEF      IOBASE + 0x000
MEMBASE:          .VDEF      IOBASE + 0x020
IOPBASE:          .VDEF      IOBASE + 0x060
INTBASE:          .VDEF      IOBASE + 0x0A0
TMBBASE:          .VDEF      IOBASE + 0x0B0
TMRBASE:          .VDEF      IOBASE + 0x0C0
AUDBASE:          .VDEF      IOBASE + 0x0E0
URTBASE:          .VDEF      IOBASE + 0x100
RTCBASE:          .VDEF      IOBASE + 0x120
SPIBASE:          .VDEF      IOBASE + 0x140
ANABASE:          .VDEF      IOBASE + 0x160
LCDBASE:          .VDEF      IOBASE + 0x180
IMSBASE:          .VDEF      IOBASE + 0x1A0
SPBBASE:          .VDEF      IOBASE + 0x1B0
TM2BASE:          .VDEF      IOBASE + 0x1C0
SDCBASE:          .VDEF      IOBASE + 0x1D0
LCPBASE:          .VDEF      IOBASE + 0x200
USBBASE:          .VDEF      IOBASE + 0x300
I2CBASE:          .VDEF      IOBASE + 0x360
DMABASE:          .VDEF      IOBASE + 0x380
KEYBASE:          .VDEF      IOBASE + 0x3C0
USB_BASE:	.VDEF	    IOBASE + 0x300
//========================================================================================
// System Control Registers
//      Base Address Start from 0x7000
//========================================================================================
P_BodyID:         .VDEF      (SYSBASE + 0x00)
P_PCLKENL:        .VDEF      (SYSBASE + 0x04)
P_PCLKENH:        .VDEF      (SYSBASE + 0x05)
P_Reset_Flag:     .VDEF      (SYSBASE + 0x06)
P_Clock_Ctrl:     .VDEF      (SYSBASE + 0x07)
P_LVR_Ctrl:       .VDEF      (SYSBASE + 0x08)
P_LVD_Ctrl:       .VDEF      (SYSBASE + 0x09)
P_WatchDog_Ctrl:  .VDEF      (SYSBASE + 0x0A)
P_WatchDog_Clear: .VDEF      (SYSBASE + 0x0B)
P_WAIT:           .VDEF      (SYSBASE + 0x0C)
P_HALT:           .VDEF      (SYSBASE + 0x0D)
P_SLEEP:          .VDEF      (SYSBASE + 0x0E)
P_Power_State:    .VDEF      (SYSBASE + 0x0F)
P_Segment_Num:    .VDEF      (SYSBASE + 0x10)
P_Pixel_Ctrl:     .VDEF      (SYSBASE + 0x11)
P_Pixel_Start_L:  .VDEF      (SYSBASE + 0x12)
P_Pixel_End_L:    .VDEF      (SYSBASE + 0x13)
P_Pixel_Start_H:  .VDEF      (SYSBASE + 0x14)
P_Pixel_End_H:    .VDEF      (SYSBASE + 0x15)
P_AD_Driving:     .VDEF      (SYSBASE + 0x1F)

//========================================================================================
//  Memory Control Registers
//      Base Address Start from 0x7020
//========================================================================================
P_CS0_Ctrl:	 .VDEF	MEMBASE + 0x0000		// CS0 Device Control Register
P_CS1_Ctrl:	 .VDEF	MEMBASE + 0x0001		// CS1 Device Control Register
P_CS2_Ctrl:	 .VDEF	MEMBASE + 0x0002		// CS2 Device Control Register
P_CS3_Ctrl:	 .VDEF  MEMBASE + 0x0003		// CS3 Device Control Register
P_CS4_Ctrl:	 .VDEF	MEMBASE + 0x0004		// CS4 Device Control Register
P_CS5_Ctrl:	 .VDEF	MEMBASE + 0x0005		// CS5 Device Control Register
P_Mem_Ctrl:	 .VDEF	MEMBASE + 0x0020		// Memory Control Register
P_ADR_Ctrl:	 .VDEF	MEMBASE + 0x0021		// Memory Address Control Register

P_CS1_Start_Addr:	 .VDEF	0x80000		// CS1 Start Address
P_CS1_End_Addr:	 .VDEF	0x100000	// CS1 End Address

//P_NFINTCtrl:	.VDEF	MEMBASE + 0x0027
P_ECCLPR_L_HB:	.VDEF	MEMBASE + 0x0028
P_ECCLPR_H_HB:	.VDEF	MEMBASE + 0x0029
P_ECCCPR_HB:	.VDEF	MEMBASE + 0x002a
P_ECCLPR_CKL_HB:	.VDEF	MEMBASE + 0x002b
P_ECCLPR_CKH_HB:	.VDEF	MEMBASE + 0x002c
P_ECCCPCKR_HB:	.VDEF	MEMBASE + 0x002d
P_ECCERR0_HB:	.VDEF	MEMBASE + 0x002e
P_ECCERR1_HB:	.VDEF	MEMBASE + 0x002f

P_NF_Ctrl:        .VDEF      (MEMBASE + 0x30)
P_NF_Command:     .VDEF      (MEMBASE + 0x31)
P_NF_AddrL:       .VDEF      (MEMBASE + 0x32)
P_NF_AddrH:       .VDEF      (MEMBASE + 0x33)
P_NF_Data:       .VDEF      (MEMBASE + 0x34)
P_NF_Int:         .VDEF      (MEMBASE + 0x35)


P_ECC_Ctrl:	.VDEF	MEMBASE + 0x0037
P_ECCLPR_L_LB:	.VDEF	MEMBASE + 0x0038
P_ECCLPR_H_LB:	.VDEF	MEMBASE + 0x0039
P_ECCCPR_LB:	.VDEF	MEMBASE + 0x003a
P_ECCLPR_CKL_LB:	.VDEF	MEMBASE + 0x003b
P_ECCLPR_CKH_LB:	.VDEF	MEMBASE + 0x003c
P_ECCCPCKR_LB:	.VDEF	MEMBASE + 0x003d
P_ECCERR0_LB:	.VDEF	MEMBASE + 0x003e
P_ECCERR1_LB:	.VDEF	MEMBASE + 0x003f

//========================================================================================
//  I/O Port Control Registers
//      Base Address Start from 0x7060
//========================================================================================

P_IOA_Data:       .VDEF      (IOPBASE + 0x00)
P_IOA_Buffer:     .VDEF      (IOPBASE + 0x01)
P_IOA_Dir:        .VDEF      (IOPBASE + 0x02)
P_IOA_Attrib:     .VDEF      (IOPBASE + 0x03)
P_IOA_Latch:      .VDEF      (IOPBASE + 0x04)
P_IOB_Data:       .VDEF      (IOPBASE + 0x08)
P_IOB_Buffer:     .VDEF      (IOPBASE + 0x09)
P_IOB_Dir:        .VDEF      (IOPBASE + 0x0A)
P_IOB_Attrib:     .VDEF      (IOPBASE + 0x0B)
P_IOB_Latch:      .VDEF      (IOPBASE + 0x0C)
P_IOC_Data:       .VDEF      (IOPBASE + 0x10)
P_IOC_Buffer:     .VDEF      (IOPBASE + 0x11)
P_IOC_Dir:        .VDEF      (IOPBASE + 0x12)
P_IOC_Attrib:     .VDEF      (IOPBASE + 0x13)
P_IOC_Latch:      .VDEF      (IOPBASE + 0x14)
P_IOD_Data:       .VDEF      (IOPBASE + 0x18)
P_IOD_Buffer:     .VDEF      (IOPBASE + 0x19)
P_IOD_Dir:        .VDEF      (IOPBASE + 0x1A)
P_IOD_Attrib:     .VDEF      (IOPBASE + 0x1B)
P_IOD_Latch:      .VDEF      (IOPBASE + 0x1C)
P_IOE_Data:       .VDEF     (IOPBASE + 0x20)
P_IOE_Buffer:     .VDEF     (IOPBASE + 0x21)
P_IOE_Dir:        .VDEF      (IOPBASE + 0x22)
P_IOE_Attrib:     .VDEF      (IOPBASE + 0x23)
P_IOE_Latch:      .VDEF      (IOPBASE + 0x24)



//========================================================================================
//  Interrupt Control Registers
//      Base Address Start from 0x70A0
//========================================================================================

P_INT_Status1:    .VDEF      (INTBASE + 0x00)
.define		C_ExitA_INT			0x0001
.define		C_ExitB_INT			0x0002
.define		C_DMA_INT			0x0004
.define		C_USB_INT			0x0008
.define		C_AudioA_INT		0x0010
.define		C_AudioB_INT		0x0020
.define		C_SPSerierBus_INT	0x0040	
.define		C_ADCautoSample_INT	0x0080
.define		C_TP_INT			0x0100
.define		C_LCDFP_INT			0x0200
.define		C_SPI_INT			0x0400
.define		C_UARTIRDA_INT		0x0800
.define		C_CMOSHalfFull_INT	0x1000
.define		C_CMOSFull_INT		0x2000
.define		C_ADCReady_INT		0x4000
.define		C_KeyChange_INT		0x8000	


P_INT_Status2:    .VDEF      (INTBASE + 0x01)
.define		C_HMS_INT			0x0001		
.define		C_Alarm_INT			0x0002
.define		C_Schedule_INT		0x0004
.define		C_ShutDown_INT		0x0008
.define		C_NANDFlash_INT		0x0010
.define		C_I2C_INT			0x0020
.define		C_SD_INT			0x0040
.define		C_LVD_INT			0x0080
.define		C_TimeBaseA_INT		0x0100
.define		C_TimeBaseB_INT		0x0200
.define		C_TimeBaseC_INT		0x0400
.define		C_KeyScan_INT		0x0800
.define		C_TimerA_INT		0x1000
.define		C_TimerB_INT		0x2000
.define		C_TimerC_INT		0x4000
.define		C_TimerD_INT		0x8000


P_INT_Priority1:  .VDEF      (INTBASE + 0x04)
P_INT_Priority2:  .VDEF      (INTBASE + 0x05)
P_MINT_Ctrl:      .VDEF      (INTBASE + 0x08)


//========================================================================================
//  TimeBase Control Registers
//      Base Address Start from 0x70B0
//========================================================================================
P_TimeBaseA_Ctrl:  .VDEF     (TMBBASE + 0x00)
P_TimeBaseB_Ctrl:  .VDEF     (TMBBASE + 0x01)
P_TimeBaseC_Ctrl:  .VDEF     (TMBBASE + 0x02)