📄 iic.asm
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//========================================================================================
// Copyright (c) 2002, Sunplus Technology Co., Ltd.
// CONFIDENTIAL INFORMATION - This information in its original or translated
// form (compiled, assembled, object module or otherwise) is CONFIDENTIAL
// INFORMATION and the property of Sunplus Technology Co., Ltd.
// Progarm: SPL16256 Sample Program
// Arranged by: Jay Lin
//========================================================================================
.PUBLIC _BREAK, _FIQ, _IRQ0, _IRQ1, _IRQ2, _IRQ3, _IRQ4, _IRQ5, _IRQ6, _IRQ7;
.PUBLIC _main;
.INCLUDE SPL162001.inc
.INCLUDE MACRO.inc
.DEFINE C_StackTop 0x6FFF
.define deviceaddr 0x0e0
.define write 0x00
.define Read 0x01
.define IIC_intflag 0x10
.ram
.var R_Error
.var R_Error1
.var R_LowAddr
.var R_HighAddr
.var R_SendData
.var R_IICFlag
.var R_TimerFlag
.var R_StoreAddr
.var R_WR
.var R_Transmit_Count
.var R_Receive_Count
.code
_main:
sp=C_StackTop
r1=0x0341
[P_CS0_Ctrl]=r1
[P_CS1_Ctrl]=r1
r1=0x8402
[P_Clock_Ctrl]=r1
r1=512/4
wait?:
r1-=1
jnz wait?
nop
r1=0x00
[R_Error]=r1
[R_Error1]=r1
[R_IICFlag]=r1
[R_TimerFlag]=r1
[R_Transmit_Count]=r1
[R_Receive_Count]=r1
nop
r1=0x0100
[R_StoreAddr]=r1
r2=0x00
clearloop?:
[r1++]=r2
cmp r1,0xa00
jne clearloop?
nop
// goto IIC_Single_Master_Write_Polling
goto IIC_Single_Master_Receive_Polling
// goto IIC_Series_WriteRead_Polling
// goto IIC_Series_WriteRead_INT
// goto IIC_Single_Slave_Write_Polling
// goto IIC_Single_Slave_Read_Polling
nop
jmp $
/////////////////////////////////////////////////////////
// IIC_Write
/////////////////////////////////////////////////////////
IIC_Single_Master_Write_Polling:
r1=0x10000-32768/100
[P_TimerA_Preload]=r1
r1=0xc062
[P_TimerA_Ctrl]=r1
r1=0x01
[P_I2CEN]=r1 // I2C Enable
irq on
r1=0x09a //clock is 75kHz, enable ACK
[P_ICCR]=r1
r1=0x010
[P_IDEBCLK]=r1
testloop:
r1=[P_ICCR]
test r1,0x010
jnz testloop
r3=0x00 // Device Address: Write
r3+=deviceaddr+write
[R_HighAddr]=r3
r1=0x00
[R_SendData]=r1
r1=0x0d0 //master tx, enable rx/tx
[P_ICSR]=r1
//writeloop:
r1=0x00
[R_IICFlag]=r1
r1=[R_HighAddr] //send device addr
[P_IDSR]=r1
r1=0x0f0
[P_ICSR]=r1 //send data
/////////////////////////////////////////////
// Wait Interrupt pending
/////////////////////////////////////////////
waitloop?:
r1=[P_ICCR]
test r1,0x010
jz waitloop?
r1=[P_ICSR]
r1&=0x0f
test r1,0x01
jz next?
r1=0x0d0
[P_ICSR]=r1
call F_Error
goto Error //ack not receive
next?:
test r1,0x08
jz next1?
r1=0x0d0
[P_ICSR]=r1
call F_Error1
goto Error
next1?:
writeloop:
next3?:
// r1=0x00
// [R_IICFlag]=r1
r1=[R_SendData]
[P_IDSR]=r1
r1=[P_ICCR] //clear int flag and send data
[P_ICCR]=r1
waitloop2?:
r1=[P_ICCR]
test r1,0x010
jz waitloop2?
r1=[P_ICSR]
r1&=0x0f
test r1,0x01
jz next4?
r1=0xd0
[P_ICSR]=r1
call F_Error
goto Error
next4?:
test r1,0x08
jz next5?
r1=0x0d0
[P_ICSR]=r1
call F_Error1
goto Error
next5?:
// r1=0x0d0 // I2C-bus interface stop signal
// [P_ICSR]=r1
// r1=[P_ICCR]
// [P_ICCR]=r1
// r1=[P_TimerA_Ctrl] //enable timera for program time, 10ms
// r1|=0x2000
// [P_TimerA_Ctrl]=r1
// nop
//proloop?:
// r1=[R_TimerFlag]
// jz proloop?
// r1=0x00
// [R_TimerFlag]=r1
// r1=[P_TimerA_Ctrl]
// r1&=(~0x2000)
// [P_TimerA_Ctrl]=r1
r1=[R_SendData]
r1+=1
[R_SendData]=r1
// r1=[R_LowAddr]
// r1+=1
// [R_LowAddr]=r1
r1=[R_Transmit_Count]
r1+=1
[R_Transmit_Count]=r1
cmp r1,0x100
// je receivetest
je Master_Transmit_Complete?
call F_Delay
goto writeloop
Master_Transmit_Complete?:
jmp $
//////////////////////////////////////////////////////////////
// IIC_Single_Master_Receive_Polling
//////////////////////////////////////////////////////////////
IIC_Single_Master_Receive_Polling:
r1=0x10000-32768/100
[P_TimerA_Preload]=r1
r1=0xc062
[P_TimerA_Ctrl]=r1
r1=0x01
[P_I2CEN]=r1 // I2C Enable
irq on
r1=0x09a //clock is 75kHz, enable ACK
[P_ICCR]=r1
r1=0x010
[P_IDEBCLK]=r1
testloop?:
r1=[P_ICCR]
test r1,0x010
jnz testloop?
// r2=0x00 //low addr byte
// [R_LowAddr]=r2
r3=0x00 //high addr byte
r3+=deviceaddr+Read
[R_HighAddr]=r3
r1=0x90 // Master receive mode
[P_ICSR]=r1
r1=[R_HighAddr] // Transmit Slave Device Address
[P_IDSR]=r1
r1=0x0b0
[P_ICSR]=r1
waitloop2?:
r1=[P_ICCR]
test r1,0x010
jz waitloop2?
r1=[P_ICSR]
r1&=0x0f
test r1,0x01
jz next4?
r1=0x90
[P_ICSR]=r1
call F_Error
goto Error
next4?:
test r1,0x08
jz next5?
r1=0x090
[P_ICSR]=r1
call F_Error1
goto Error
next5?:
/////////////////////////////
//linloop:
// r1=[P_ICCR]
// r1&=(~0x80)
// [P_ICCR]=r1
//lwaitloop2?:
// r1=[P_ICCR]
// test r1,0x010
// jz lwaitloop2?
nop
nop
// jmp linloop
///////////////////////////////////
r1=[P_IDSR]
readloop:
// r1=0x00
// [P_IDSR]=r1
r1=[P_ICCR] //clear int flag and send data
[P_ICCR]=r1
waitloop3?:
r1=[P_ICCR]
test r1,0x010
jz waitloop3?
r1=[P_ICSR]
r1&=0x0f
test r1,0x01
jz next6?
r1=0x90
[P_ICSR]=r1
call F_Error
goto Error
next6?:
test r1,0x08
jz next7?
r1=0x090
[P_ICSR]=r1
call F_Error1
goto Error
next7?:
r1=[P_IDSR]
r2=[R_StoreAddr]
[r2++]=r1
[R_StoreAddr]=r2
// r1=0x090
// [P_ICSR]=r1
// r1=[P_ICCR]
// r1|=0x80
// [P_ICCR]=r1
// r1=[R_LowAddr]
// r1+=1
// [R_LowAddr]=r1
r1=[R_Receive_Count]
r1+=1
[R_Receive_Count]=r1
cmp r1,0x100
// je judge
je Master_Receive_Complete?
call F_Delay
goto readloop
Master_Receive_Complete?:
Compare?:
r1=0x80
r2=0x100
judgeloop?:
r3=[r2++]
cmp r3,r1
je skip?
call F_Error
skip?:
r1+=1
cmp r1,0x100
jne judgeloop?
nop
jmp $ //test ok
///////////////////////////////////////////////////////////////
//IIC_Single_Slave_Write_Polling
///////////////////////////////////////////////////////////////
IIC_Single_Slave_Write_Polling:
r1=0x10000-32768/100
[P_TimerA_Preload]=r1
r1=0xc062
[P_TimerA_Ctrl]=r1
r1=0x01
[P_I2CEN]=r1 // I2C Enable
irq on
r1=0x09a //clock is 75kHz, enable ACK
[P_ICCR]=r1
r1=0x010
[P_IDEBCLK]=r1
testloop?:
r1=[P_ICCR]
test r1,0x010
jnz testloop?
r3=0x00
r3+=deviceaddr+write
// [R_HighAddr]=r3
[P_IAR]=r3
r1=0x80
[R_SendData]=r1
r1=0x50 // change to slave transmit mode
[P_ICSR]=r1
wait_IAR_Match?:
r1=[P_ICSR]
r1&=0x0f
cmp r1, 0x04
jnz wait_IAR_Match?
waitloop?:
r1=[P_ICCR]
test r1,0x010
jz waitloop?
Slave_writeloop:
r3=[R_SendData]
[P_IDSR]=r3
r1=[P_ICCR] //clear int flag and send data
[P_ICCR]=r1
waitloop1?:
r1=[P_ICCR]
test r1,0x010
jz waitloop1?
r1=[P_ICSR]
r1&=0x0f
test r1,0x01
jz next2?
r1=0x050
[P_ICSR]=r1
call F_Error
goto Error
next2?:
test r1,0x08
jz next3?
r1=0x0d0
[P_ICSR]=r1
call F_Error1
goto Error
next3?:
r3=[R_SendData]
r3+=1
[R_SendData]=r3
r1=[R_Transmit_Count]
r1+=1
[R_Transmit_Count]=r1
cmp r1, 0x100
je Slave_Transmit_Complete?
call F_Delay
goto Slave_writeloop
Slave_Transmit_Complete?:
jmp $
///////////////////////////////////////////////////////////////
// IIC_Single_Slave_Read_Polling
///////////////////////////////////////////////////////////////
IIC_Single_Slave_Read_Polling:
r1=0x10000-32768/100
[P_TimerA_Preload]=r1
r1=0xc062
[P_TimerA_Ctrl]=r1
r1=0x01
[P_I2CEN]=r1 // I2C Enable
irq on
r1=0x09a //clock is 75kHz, enable ACK
[P_ICCR]=r1
r1=0x010
[P_IDEBCLK]=r1
testloop?:
r1=[P_ICCR]
test r1,0x010
jnz testloop?
r3=0x00
r3+=deviceaddr
[P_IAR]=r3 // Write Slave Address to IAR
r1=0x10 // change to slave receive mode
[P_ICSR]=r1
wait_IAR_Match?:
r1=[P_ICSR]
r1&=0x0f
cmp r1, 0x04
jnz wait_IAR_Match?
waitloop?:
r1=[P_ICCR]
test r1,0x010
jz waitloop?
r1=[P_IDSR]
Slave_Readloop:
r1=[P_ICCR] //clear int flag and receive data
[P_ICCR]=r1
waitloop3?:
r1=[P_ICCR]
test r1,0x010
jz waitloop3?
r1=[P_ICSR]
r1&=0x0f
test r1,0x01
jz next6?
r1=0x10
[P_ICSR]=r1
call F_Error
goto Error
next6?:
test r1,0x08
jz next7?
r1=0x010
[P_ICSR]=r1
call F_Error1
goto Error
next7?:
r1=[P_IDSR]
r2=[R_StoreAddr]
[r2++]=r1
[R_StoreAddr]=r2
// r1=0x090
// [P_ICSR]=r1
// r1=[P_ICCR]
// r1|=0x80
// [P_ICCR]=r1
// r1=[R_LowAddr]
// r1+=1
// [R_LowAddr]=r1
r1=[R_Receive_Count]
r1+=1
[R_Receive_Count]=r1
cmp r1,0x100
je Slave_Receive_Complete?
call F_Delay
goto Slave_Readloop
Slave_Receive_Complete?:
jmp $
///////////////////////////////////////////////////////////////
// IIC_Series_WriteRead
//////////////////////////////////////////////////////////////
IIC_Series_WriteRead_Polling:
r1=0x10000-32768/100
[P_TimerA_Preload]=r1
r1=0x01
[P_I2CEN]=r1
r1=0xc062
[P_TimerA_Ctrl]=r1
irq on
r1=0x09a //clock is 75kHz, enable ACK
[P_ICCR]=r1
r1=0x010
[P_IDEBCLK]=r1
///////////////////////////////////////////////////////////
r2=0x00 //low addr byte
[R_LowAddr]=r2
r3=0x00 //high addr byte
r3+=deviceaddr+write
[R_HighAddr]=r3
r1=0x080
[R_SendData]=r1
r1=0x0d0
[P_ICSR]=r1
serieswriteloop:
r1=0x00
[R_IICFlag]=r1
r1=[R_HighAddr] //send device addr
[P_IDSR]=r1
r1=0x0f0
[P_ICSR]=r1 //send data
waitloop?:
r1=[P_ICCR]
test r1,0x010
jz waitloop?
r1=[P_ICSR]
r1&=0x0f
test r1,0x01
jz next?
r1=0x0d0
[P_ICSR]=r1
call F_Error
goto Error //ack not receive
next?:
test r1,0x08
jz next1?
r1=0x0d0
[P_ICSR]=r1
call F_Error1
goto Error
next1?:
r1=0x00
[R_IICFlag]=r1
r1=[R_LowAddr]
[P_IDSR]=r1
r1=[P_ICCR]
[P_ICCR]=r1
waitloop1?:
r1=[P_ICCR]
test r1,0x010
jz waitloop1?
r1=[P_ICSR]
r1&=0x0f
test r1,0x01
jz next2?
r1=0x0d0
[P_ICSR]=r1
call F_Error
goto Error
next2?:
test r1,0x08
jz next3?
r1=0x0d0
[P_ICSR]=r1
call F_Error1
goto Error
next3?:
r2=16
seriessend?:
r1=0x00
[R_IICFlag]=r1
r1=[R_SendData]
[P_IDSR]=r1
r1=[P_ICCR]
[P_ICCR]=r1
nop
waitloop2?:
r1=[P_ICCR]
test r1,0x010
jz waitloop2?
r1=[P_ICSR]
r1&=0x0f
test r1,0x01
jz next4?
r1=0xd0
[P_ICSR]=r1
call F_Error
goto Error
next4?:
test r1,0x08
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