prev_cmp_unsignmulti.map.qmsg

ALTERA上DE2平台

{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/alt_u_div_mve.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file db/alt_u_div_mve.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 alt_u_div_mve " "Info: Found entity 1: alt_u_div_mve" {  } { { "db/alt_u_div_mve.tdf" "" { Text "D:/PROGRAMING/fpga/UnsignMulti/db/alt_u_div_mve.tdf" 26 1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0}
{ "Info" "ISGN_ELABORATION_HEADER" "BinToDec:BTD0\|lpm_divide:Div1 " "Info: Elaborated megafunction instantiation \"BinToDec:BTD0\|lpm_divide:Div1\"" {  } { { "UnsignMulti.v" "" { Text "D:/PROGRAMING/fpga/UnsignMulti/UnsignMulti.v" 76 -1 0 } }  } 0 0 "Elaborated megafunction instantiation \"%1!s!\"" 0 0 "" 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/lpm_divide_0dm.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file db/lpm_divide_0dm.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 lpm_divide_0dm " "Info: Found entity 1: lpm_divide_0dm" {  } { { "db/lpm_divide_0dm.tdf" "" { Text "D:/PROGRAMING/fpga/UnsignMulti/db/lpm_divide_0dm.tdf" 24 1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0}
{ "Info" "ISGN_ELABORATION_HEADER" "BinToDec:BTD0\|lpm_divide:Div0 " "Info: Elaborated megafunction instantiation \"BinToDec:BTD0\|lpm_divide:Div0\"" {  } { { "UnsignMulti.v" "" { Text "D:/PROGRAMING/fpga/UnsignMulti/UnsignMulti.v" 75 -1 0 } }  } 0 0 "Elaborated megafunction instantiation \"%1!s!\"" 0 0 "" 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/lpm_divide_4dm.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file db/lpm_divide_4dm.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 lpm_divide_4dm " "Info: Found entity 1: lpm_divide_4dm" {  } { { "db/lpm_divide_4dm.tdf" "" { Text "D:/PROGRAMING/fpga/UnsignMulti/db/lpm_divide_4dm.tdf" 24 1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0}
{ "Info" "ISGN_ELABORATION_HEADER" "BinToDec:BTD1\|lpm_divide:Mod0 " "Info: Elaborated megafunction instantiation \"BinToDec:BTD1\|lpm_divide:Mod0\"" {  } { { "UnsignMulti.v" "" { Text "D:/PROGRAMING/fpga/UnsignMulti/UnsignMulti.v" 76 -1 0 } }  } 0 0 "Elaborated megafunction instantiation \"%1!s!\"" 0 0 "" 0}
{ "Info" "IOPT_MLS_DUP_REG_INFO_HDR" "" "Info: Duplicate registers merged to single register" { { "Info" "IOPT_MLS_DUP_REG_INFO" "DecDis:DD2\|HexVal\[3\] DecDis:DD2\|HexVal\[0\] " "Info: Duplicate register \"DecDis:DD2\|HexVal\[3\]\" merged to single register \"DecDis:DD2\|HexVal\[0\]\"" {  } { { "UnsignMulti.v" "" { Text "D:/PROGRAMING/fpga/UnsignMulti/UnsignMulti.v" 92 -1 0 } }  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0 "" 0}  } {  } 0 0 "Duplicate registers merged to single register" 0 0 "" 0}
{ "Info" "ICDB_SGATE_CDB_INFO_USING_PWRUP_DC" "DecDis:DD10\|HexVal\[6\] High " "Info: Power-up level of register \"DecDis:DD10\|HexVal\[6\]\" is not specified -- using power-up level of High to minimize register" {  } { { "UnsignMulti.v" "" { Text "D:/PROGRAMING/fpga/UnsignMulti/UnsignMulti.v" 92 -1 0 } }  } 0 0 "Power-up level of register \"%1!s!\" is not specified -- using power-up level of %2!s! to minimize register" 0 0 "" 0}
{ "Warning" "WCDB_SGATE_CDB_WARN_TRIVIAL_REG" "DecDis:DD10\|HexVal\[6\] data_in VCC " "Warning (14130): Reduced register \"DecDis:DD10\|HexVal\[6\]\" with stuck data_in port to stuck value VCC" {  } { { "UnsignMulti.v" "" { Text "D:/PROGRAMING/fpga/UnsignMulti/UnsignMulti.v" 92 -1 0 } }  } 0 14130 "Reduced register \"%1!s!\" with stuck %2!s! port to stuck value %3!s!" 0 0 "" 0}
{ "Info" "ICDB_SGATE_CDB_INFO_USING_PWRUP_DC" "DecDis:DD20\|HexVal\[6\] High " "Info: Power-up level of register \"DecDis:DD20\|HexVal\[6\]\" is not specified -- using power-up level of High to minimize register" {  } { { "UnsignMulti.v" "" { Text "D:/PROGRAMING/fpga/UnsignMulti/UnsignMulti.v" 92 -1 0 } }  } 0 0 "Power-up level of register \"%1!s!\" is not specified -- using power-up level of %2!s! to minimize register" 0 0 "" 0}
{ "Warning" "WCDB_SGATE_CDB_WARN_TRIVIAL_REG" "DecDis:DD20\|HexVal\[6\] data_in VCC " "Warning (14130): Reduced register \"DecDis:DD20\|HexVal\[6\]\" with stuck data_in port to stuck value VCC" {  } { { "UnsignMulti.v" "" { Text "D:/PROGRAMING/fpga/UnsignMulti/UnsignMulti.v" 92 -1 0 } }  } 0 14130 "Reduced register \"%1!s!\" with stuck %2!s! port to stuck value %3!s!" 0 0 "" 0}
{ "Info" "IOPT_MLS_DUP_REG_INFO_HDR" "" "Info: Duplicate registers merged to single register" { { "Info" "IOPT_MLS_DUP_REG_INFO" "DecDis:DD20\|HexVal\[2\] DecDis:DD20\|HexVal\[1\] " "Info: Duplicate register \"DecDis:DD20\|HexVal\[2\]\" merged to single register \"DecDis:DD20\|HexVal\[1\]\"" {  } { { "UnsignMulti.v" "" { Text "D:/PROGRAMING/fpga/UnsignMulti/UnsignMulti.v" 92 -1 0 } }  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0 "" 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "DecDis:DD20\|HexVal\[1\] DecDis:DD10\|HexVal\[2\] " "Info: Duplicate register \"DecDis:DD20\|HexVal\[1\]\" merged to single register \"DecDis:DD10\|HexVal\[2\]\"" {  } { { "UnsignMulti.v" "" { Text "D:/PROGRAMING/fpga/UnsignMulti/UnsignMulti.v" 92 -1 0 } }  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0 "" 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "DecDis:DD10\|HexVal\[2\] DecDis:DD10\|HexVal\[1\] " "Info: Duplicate register \"DecDis:DD10\|HexVal\[2\]\" merged to single register \"DecDis:DD10\|HexVal\[1\]\"" {  } { { "UnsignMulti.v" "" { Text "D:/PROGRAMING/fpga/UnsignMulti/UnsignMulti.v" 92 -1 0 } }  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0 "" 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "DecDis:DD10\|HexVal\[1\] DecDis:DD2\|HexVal\[1\] " "Info: Duplicate register \"DecDis:DD10\|HexVal\[1\]\" merged to single register \"DecDis:DD2\|HexVal\[1\]\"" {  } { { "UnsignMulti.v" "" { Text "D:/PROGRAMING/fpga/UnsignMulti/UnsignMulti.v" 92 -1 0 } }  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0 "" 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "DecDis:DD10\|HexVal\[4\] DecDis:DD10\|HexVal\[0\] " "Info: Duplicate register \"DecDis:DD10\|HexVal\[4\]\" merged to single register \"DecDis:DD10\|HexVal\[0\]\"" {  } { { "UnsignMulti.v" "" { Text "D:/PROGRAMING/fpga/UnsignMulti/UnsignMulti.v" 92 -1 0 } }  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0 "" 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "DecDis:DD10\|HexVal\[3\] DecDis:DD10\|HexVal\[0\] " "Info: Duplicate register \"DecDis:DD10\|HexVal\[3\]\" merged to single register \"DecDis:DD10\|HexVal\[0\]\"" {  } { { "UnsignMulti.v" "" { Text "D:/PROGRAMING/fpga/UnsignMulti/UnsignMulti.v" 92 -1 0 } }  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0 "" 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "DecDis:DD10\|HexVal\[5\] DecDis:DD10\|HexVal\[0\] " "Info: Duplicate register \"DecDis:DD10\|HexVal\[5\]\" merged to single register \"DecDis:DD10\|HexVal\[0\]\"" {  } { { "UnsignMulti.v" "" { Text "D:/PROGRAMING/fpga/UnsignMulti/UnsignMulti.v" 92 -1 0 } }  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0 "" 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "DecDis:DD20\|HexVal\[4\] DecDis:DD20\|HexVal\[0\] " "Info: Duplicate register \"DecDis:DD20\|HexVal\[4\]\" merged to single register \"DecDis:DD20\|HexVal\[0\]\"" {  } { { "UnsignMulti.v" "" { Text "D:/PROGRAMING/fpga/UnsignMulti/UnsignMulti.v" 92 -1 0 } }  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0 "" 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "DecDis:DD20\|HexVal\[3\] DecDis:DD20\|HexVal\[0\] " "Info: Duplicate register \"DecDis:DD20\|HexVal\[3\]\" merged to single register \"DecDis:DD20\|HexVal\[0\]\"" {  } { { "UnsignMulti.v" "" { Text "D:/PROGRAMING/fpga/UnsignMulti/UnsignMulti.v" 92 -1 0 } }  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0 "" 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "DecDis:DD20\|HexVal\[5\] DecDis:DD20\|HexVal\[0\] " "Info: Duplicate register \"DecDis:DD20\|HexVal\[5\]\" merged to single register \"DecDis:DD20\|HexVal\[0\]\"" {  } { { "UnsignMulti.v" "" { Text "D:/PROGRAMING/fpga/UnsignMulti/UnsignMulti.v" 92 -1 0 } }  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0 "" 0}  } {  } 0 0 "Duplicate registers merged to single register" 0 0 "" 0}
{ "Info" "IOPT_MLS_PRESET_POWER_UP" "" "Info: Registers with preset signals will power-up high" {  } { { "UnsignMulti.v" "" { Text "D:/PROGRAMING/fpga/UnsignMulti/UnsignMulti.v" 92 -1 0 } } { "UnsignMulti.v" "" { Text "D:/PROGRAMING/fpga/UnsignMulti/UnsignMulti.v" 92 -1 0 } } { "UnsignMulti.v" "" { Text "D:/PROGRAMING/fpga/UnsignMulti/UnsignMulti.v" 92 -1 0 } } { "UnsignMulti.v" "" { Text "D:/PROGRAMING/fpga/UnsignMulti/UnsignMulti.v" 92 -1 0 } } { "UnsignMulti.v" "" { Text "D:/PROGRAMING/fpga/UnsignMulti/UnsignMulti.v" 92 -1 0 } } { "UnsignMulti.v" "" { Text "D:/PROGRAMING/fpga/UnsignMulti/UnsignMulti.v" 92 -1 0 } } { "UnsignMulti.v" "" { Text "D:/PROGRAMING/fpga/UnsignMulti/UnsignMulti.v" 92 -1 0 } } { "UnsignMulti.v" "" { Text "D:/PROGRAMING/fpga/UnsignMulti/UnsignMulti.v" 92 -1 0 } } { "UnsignMulti.v" "" { Text "D:/PROGRAMING/fpga/UnsignMulti/UnsignMulti.v" 92 -1 0 } } { "UnsignMulti.v" "" { Text "D:/PROGRAMING/fpga/UnsignMulti/UnsignMulti.v" 92 -1 0 } } { "UnsignMulti.v" "" { Text "D:/PROGRAMING/fpga/UnsignMulti/UnsignMulti.v" 92 -1 0 } } { "UnsignMulti.v" "" { Text "D:/PROGRAMING/fpga/UnsignMulti/UnsignMulti.v" 92 -1 0 } } { "UnsignMulti.v" "" { Text "D:/PROGRAMING/fpga/UnsignMulti/UnsignMulti.v" 92 -1 0 } } { "UnsignMulti.v" "" { Text "D:/PROGRAMING/fpga/UnsignMulti/UnsignMulti.v" 92 -1 0 } } { "UnsignMulti.v" "" { Text "D:/PROGRAMING/fpga/UnsignMulti/UnsignMulti.v" 92 -1 0 } } { "UnsignMulti.v" "" { Text "D:/PROGRAMING/fpga/UnsignMulti/UnsignMulti.v" 92 -1 0 } } { "UnsignMulti.v" "" { Text "D:/PROGRAMING/fpga/UnsignMulti/UnsignMulti.v" 92 -1 0 } } { "UnsignMulti.v" "" { Text "D:/PROGRAMING/fpga/UnsignMulti/UnsignMulti.v" 92 -1 0 } } { "UnsignMulti.v" "" { Text "D:/PROGRAMING/fpga/UnsignMulti/UnsignMulti.v" 92 -1 0 } } { "UnsignMulti.v" "" { Text "D:/PROGRAMING/fpga/UnsignMulti/UnsignMulti.v" 92 -1 0 } } { "UnsignMulti.v" "" { Text "D:/PROGRAMING/fpga/UnsignMulti/UnsignMulti.v" 92 -1 0 } } { "UnsignMulti.v" "" { Text "D:/PROGRAMING/fpga/UnsignMulti/UnsignMulti.v" 92 -1 0 } } { "UnsignMulti.v" "" { Text "D:/PROGRAMING/fpga/UnsignMulti/UnsignMulti.v" 92 -1 0 } } { "UnsignMulti.v" "" { Text "D:/PROGRAMING/fpga/UnsignMulti/UnsignMulti.v" 92 -1 0 } } { "UnsignMulti.v" "" { Text "D:/PROGRAMING/fpga/UnsignMulti/UnsignMulti.v" 92 -1 0 } } { "UnsignMulti.v" "" { Text "D:/PROGRAMING/fpga/UnsignMulti/UnsignMulti.v" 92 -1 0 } } { "UnsignMulti.v" "" { Text "D:/PROGRAMING/fpga/UnsignMulti/UnsignMulti.v" 92 -1 0 } } { "UnsignMulti.v" "" { Text "D:/PROGRAMING/fpga/UnsignMulti/UnsignMulti.v" 92 -1 0 } } { "UnsignMulti.v" "" { Text "D:/PROGRAMING/fpga/UnsignMulti/UnsignMulti.v" 92 -1 0 } } { "UnsignMulti.v" "" { Text "D:/PROGRAMING/fpga/UnsignMulti/UnsignMulti.v" 92 -1 0 } } { "UnsignMulti.v" "" { Text "D:/PROGRAMING/fpga/UnsignMulti/UnsignMulti.v" 92 -1 0 } } { "UnsignMulti.v" "" { Text "D:/PROGRAMING/fpga/UnsignMulti/UnsignMulti.v" 92 -1 0 } } { "UnsignMulti.v" "" { Text "D:/PROGRAMING/fpga/UnsignMulti/UnsignMulti.v" 92 -1 0 } } { "UnsignMulti.v" "" { Text "D:/PROGRAMING/fpga/UnsignMulti/UnsignMulti.v" 92 -1 0 } } { "UnsignMulti.v" "" { Text "D:/PROGRAMING/fpga/UnsignMulti/UnsignMulti.v" 92 -1 0 } } { "UnsignMulti.v" "" { Text "D:/PROGRAMING/fpga/UnsignMulti/UnsignMulti.v" 92 -1 0 } }  } 0 0 "Registers with preset signals will power-up high" 0 0 "" 0}
{ "Info" "IOPT_MLS_DEV_CLRN_SETS_REGISTERS" "" "Info: DEV_CLRn pin will set, and not reset, register with preset signal due to NOT Gate Push-Back" {  } {  } 0 0 "DEV_CLRn pin will set, and not reset, register with preset signal due to NOT Gate Push-Back" 0 0 "" 0}
{ "Warning" "WOPT_MLS_STUCK_PIN_HDR" "" "Warning: Output pins are stuck at VCC or GND" { { "Warning" "WOPT_MLS_STUCK_PIN" "LEDR\[4\] GND " "Warning (13410): Pin \"LEDR\[4\]\" stuck at GND" {  } { { "UnsignMulti.v" "" { Text "D:/PROGRAMING/fpga/UnsignMulti/UnsignMulti.v" 8 -1 0 } }  } 0 13410 "Pin \"%1!s!\" stuck at %2!s!" 0 0 "" 0} { "Warning" "WOPT_MLS_STUCK_PIN" "LEDR\[5\] GND " "Warning (13410): Pin \"LEDR\[5\]\" stuck at GND" {  } { { "UnsignMulti.v" "" { Text "D:/PROGRAMING/fpga/UnsignMulti/UnsignMulti.v" 8 -1 0 } }  } 0 13410 "Pin \"%1!s!\" stuck at %2!s!" 0 0 "" 0} { "Warning" "WOPT_MLS_STUCK_PIN" "LEDR\[6\] GND " "Warning (13410): Pin \"LEDR\[6\]\" stuck at GND" {  } { { "UnsignMulti.v" "" { Text "D:/PROGRAMING/fpga/UnsignMulti/UnsignMulti.v" 8 -1 0 } }  } 0 13410 "Pin \"%1!s!\" stuck at %2!s!" 0 0 "" 0} { "Warning" "WOPT_MLS_STUCK_PIN" "LEDR\[7\] GND " "Warning (13410): Pin \"LEDR\[7\]\" stuck at GND" {  } { { "UnsignMulti.v" "" { Text "D:/PROGRAMING/fpga/UnsignMulti/UnsignMulti.v" 8 -1 0 } }  } 0 13410 "Pin \"%1!s!\" stuck at %2!s!" 0 0 "" 0} { "Warning" "WOPT_MLS_STUCK_PIN" "LEDR\[8\] GND " "Warning (13410): Pin \"LEDR\[8\]\" stuck at GND" {  } { { "UnsignMulti.v" "" { Text "D:/PROGRAMING/fpga/UnsignMulti/UnsignMulti.v" 8 -1 0 } }  } 0 13410 "Pin \"%1!s!\" stuck at %2!s!" 0 0 "" 0} { "Warning" "WOPT_MLS_STUCK_PIN" "LEDR\[9\] GND " "Warning (13410): Pin \"LEDR\[9\]\" stuck at GND" {  } { { "UnsignMulti.v" "" { Text "D:/PROGRAMING/fpga/UnsignMulti/UnsignMulti.v" 8 -1 0 } }  } 0 13410 "Pin \"%1!s!\" stuck at %2!s!" 0 0 "" 0} { "Warning" "WOPT_MLS_STUCK_PIN" "LEDR\[14\] GND " "Warning (13410): Pin \"LEDR\[14\]\" stuck at GND" {  } { { "UnsignMulti.v" "" { Text "D:/PROGRAMING/fpga/UnsignMulti/UnsignMulti.v" 8 -1 0 } }  } 0 13410 "Pin \"%1!s!\" stuck at %2!s!" 0 0 "" 0} { "Warning" "WOPT_MLS_STUCK_PIN" "LEDR\[15\] GND " "Warning (13410): Pin \"LEDR\[15\]\" stuck at GND" {  } { { "UnsignMulti.v" "" { Text "D:/PROGRAMING/fpga/UnsignMulti/UnsignMulti.v" 8 -1 0 } }  } 0 13410 "Pin \"%1!s!\" stuck at %2!s!" 0 0 "" 0} { "Warning" "WOPT_MLS_STUCK_PIN" "LEDR\[16\] GND " "Warning (13410): Pin \"LEDR\[16\]\" stuck at GND" {  } { { "UnsignMulti.v" "" { Text "D:/PROGRAMING/fpga/UnsignMulti/UnsignMulti.v" 8 -1 0 } }  } 0 13410 "Pin \"%1!s!\" stuck at %2!s!" 0 0 "" 0} { "Warning" "WOPT_MLS_STUCK_PIN" "LEDR\[17\] GND " "Warning (13410): Pin \"LEDR\[17\]\" stuck at GND" {  } { { "UnsignMulti.v" "" { Text "D:/PROGRAMING/fpga/UnsignMulti/UnsignMulti.v" 8 -1 0 } }  } 0 13410 "Pin \"%1!s!\" stuck at %2!s!" 0 0 "" 0} { "Warning" "WOPT_MLS_STUCK_PIN" "LEDG\[8\] GND " "Warning (13410): Pin \"LEDG\[8\]\" stuck at GND" {  } { { "UnsignMulti.v" "" { Text "D:/PROGRAMING/fpga/UnsignMulti/UnsignMulti.v" 9 -1 0 } }  } 0 13410 "Pin \"%1!s!\" stuck at %2!s!" 0 0 "" 0} { "Warning" "WOPT_MLS_STUCK_PIN" "HEX3\[0\] VCC " "Warning (13410): Pin \"HEX3\[0\]\" stuck at VCC" {  } { { "UnsignMulti.v" "" { Text "D:/PROGRAMING/fpga/UnsignMulti/UnsignMulti.v" 10 -1 0 } }  } 0 13410 "Pin \"%1!s!\" stuck at %2!s!" 0 0 "" 0} { "Warning" "WOPT_MLS_STUCK_PIN" "HEX3\[1\] VCC " "Warning (13410): Pin \"HEX3\[1\]\" stuck at VCC" {  } { { "UnsignMulti.v" "" { Text "D:/PROGRAMING/fpga/UnsignMulti/UnsignMulti.v" 10 -1 0 } }  } 0 13410 "Pin \"%1!s!\" stuck at %2!s!" 0 0 "" 0} { "Warning" "WOPT_MLS_STUCK_PIN" "HEX3\[2\] VCC " "Warning (13410): Pin \"HEX3\[2\]\" stuck at VCC" {  } { { "UnsignMulti.v" "" { Text "D:/PROGRAMING/fpga/UnsignMulti/UnsignMulti.v" 10 -1 0 } }  } 0 13410 "Pin \"%1!s!\" stuck at %2!s!" 0 0 "" 0} { "Warning" "WOPT_MLS_STUCK_PIN" "HEX3\[3\] VCC " "Warning (13410): Pin \"HEX3\[3\]\" stuck at VCC" {  } { { "UnsignMulti.v" "" { Text "D:/PROGRAMING/fpga/UnsignMulti/UnsignMulti.v" 10 -1 0 } }  } 0 13410 "Pin \"%1!s!\" stuck at %2!s!" 0 0 "" 0} { "Warning" "WOPT_MLS_STUCK_PIN" "HEX3\[4\] VCC " "Warning (13410): Pin \"HEX3\[4\]\" stuck at VCC" {  } { { "UnsignMulti.v" "" { Text "D:/PROGRAMING/fpga/UnsignMulti/UnsignMulti.v" 10 -1 0 } }  } 0 13410 "Pin \"%1!s!\" stuck at %2!s!" 0 0 "" 0} { "Warning" "WOPT_MLS_STUCK_PIN" "HEX3\[5\] VCC " "Warning (13410): Pin \"HEX3\[5\]\" stuck at VCC" {  } { { "UnsignMulti.v" "" { Text "D:/PROGRAMING/fpga/UnsignMulti/UnsignMulti.v" 10 -1 0 } }  } 0 13410 "Pin \"%1!s!\" stuck at %2!s!" 0 0 "" 0} { "Warning" "WOPT_MLS_STUCK_PIN" "HEX3\[6\] VCC " "Warning (13410): Pin \"HEX3\[6\]\" stuck at VCC" {  } { { "UnsignMulti.v" "" { Text "D:/PROGRAMING/fpga/UnsignMulti/UnsignMulti.v" 10 -1 0 } }  } 0 13410 "Pin \"%1!s!\" stuck at %2!s!" 0 0 "" 0} { "Warning" "WOPT_MLS_STUCK_PIN" "HEX5\[6\] VCC " "Warning (13410): Pin \"HEX5\[6\]\" stuck at VCC" {  } { { "UnsignMulti.v" "" { Text "D:/PROGRAMING/fpga/UnsignMulti/UnsignMulti.v" 10 -1 0 } }  } 0 13410 "Pin \"%1!s!\" stuck at %2!s!" 0 0 "" 0} { "Warning" "WOPT_MLS_STUCK_PIN" "HEX7\[6\] VCC " "Warning (13410): Pin \"HEX7\[6\]\" stuck at VCC" {  } { { "UnsignMulti.v" "" { Text "D:/PROGRAMING/fpga/UnsignMulti/UnsignMulti.v" 10 -1 0 } }  } 0 13410 "Pin \"%1!s!\" stuck at %2!s!" 0 0 "" 0}  } {  } 0 0 "Output pins are stuck at VCC or GND" 0 0 "" 0}
{ "Info" "ISCL_SCL_WANNA_REM_USR_WIRE" "" "Info: Found the following redundant logic cells in design" { { "Info" "ISCL_SCL_CELL_NAME" "BinToDec:BTD1\|lpm_divide:Mod1\|lpm_divide_35m:auto_generated\|sign_div_unsign_akh:divider\|alt_u_div_mve:divider\|add_sub_6_result_int\[0\]~12 " "Info (17048): Logic cell \"BinToDec:BTD1\|lpm_divide:Mod1\|lpm_divide_35m:auto_generated\|sign_div_unsign_akh:divider\|alt_u_div_mve:divider\|add_sub_6_result_int\[0\]~12\"" {  } { { "db/alt_u_div_mve.tdf" "add_sub_6_result_int\[0\]~12" { Text "D:/PROGRAMING/fpga/UnsignMulti/db/alt_u_div_mve.tdf" 57 22 0 } }  } 0 17048 "Logic cell \"%1!s!\"" 0 0 "" 0} { "Info" "ISCL_SCL_CELL_NAME" "BinToDec:BTD2\|lpm_divide:Mod1\|lpm_divide_35m:auto_generated\|sign_div_unsign_akh:divider\|alt_u_div_mve:divider\|add_sub_6_result_int\[0\]~12 " "Info (17048): Logic cell \"BinToDec:BTD2\|lpm_divide:Mod1\|lpm_divide_35m:auto_generated\|sign_div_unsign_akh:divider\|alt_u_div_mve:divider\|add_sub_6_result_int\[0\]~12\"" {  } { { "db/alt_u_div_mve.tdf" "add_sub_6_result_int\[0\]~12" { Text "D:/PROGRAMING/fpga/UnsignMulti/db/alt_u_div_mve.tdf" 57 22 0 } }  } 0 17048 "Logic cell \"%1!s!\"" 0 0 "" 0}  } {  } 0 0 "Found the following redundant logic cells in design" 0 0 "" 0}
{ "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN_HDR" "12 " "Warning: Design contains 12 input pin(s) that do not drive logic" { { "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN" "SW\[4\] " "Warning (15610): No output dependent on input pin \"SW\[4\]\"" {  } { { "UnsignMulti.v" "" { Text "D:/PROGRAMING/fpga/UnsignMulti/UnsignMulti.v" 6 -1 0 } }  } 0 15610 "No output dependent on input pin \"%1!s!\"" 0 0 "" 0} { "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN" "SW\[5\] " "Warning (15610): No output dependent on input pin \"SW\[5\]\"" {  } { { "UnsignMulti.v" "" { Text "D:/PROGRAMING/fpga/UnsignMulti/UnsignMulti.v" 6 -1 0 } }  } 0 15610 "No output dependent on input pin \"%1!s!\"" 0 0 "" 0} { "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN" "SW\[6\] " "Warning (15610): No output dependent on input pin \"SW\[6\]\"" {  } { { "UnsignMulti.v" "" { Text "D:/PROGRAMING/fpga/UnsignMulti/UnsignMulti.v" 6 -1 0 } }  } 0 15610 "No output dependent on input pin \"%1!s!\"" 0 0 "" 0} { "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN" "SW\[7\] " "Warning (15610): No output dependent on input pin \"SW\[7\]\"" {  } { { "UnsignMulti.v" "" { Text "D:/PROGRAMING/fpga/UnsignMulti/UnsignMulti.v" 6 -1 0 } }  } 0 15610 "No output dependent on input pin \"%1!s!\"" 0 0 "" 0} { "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN" "SW\[8\] " "Warning (15610): No output dependent on input pin \"SW\[8\]\"" {  } { { "UnsignMulti.v" "" { Text "D:/PROGRAMING/fpga/UnsignMulti/UnsignMulti.v" 6 -1 0 } }  } 0 15610 "No output dependent on input pin \"%1!s!\"" 0 0 "" 0} { "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN" "SW\[9\] " "Warning (15610): No output dependent on input pin \"SW\[9\]\"" {  } { { "UnsignMulti.v" "" { Text "D:/PROGRAMING/fpga/UnsignMulti/UnsignMulti.v" 6 -1 0 } }  } 0 15610 "No output dependent on input pin \"%1!s!\"" 0 0 "" 0} { "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN" "SW\[14\] " "Warning (15610): No output dependent on input pin \"SW\[14\]\"" {  } { { "UnsignMulti.v" "" { Text "D:/PROGRAMING/fpga/UnsignMulti/UnsignMulti.v" 6 -1 0 } }  } 0 15610 "No output dependent on input pin \"%1!s!\"" 0 0 "" 0} { "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN" "SW\[15\] " "Warning (15610): No output dependent on input pin \"SW\[15\]\"" {  } { { "UnsignMulti.v" "" { Text "D:/PROGRAMING/fpga/UnsignMulti/UnsignMulti.v" 6 -1 0 } }  } 0 15610 "No output dependent on input pin \"%1!s!\"" 0 0 "" 0} { "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN" "SW\[16\] " "Warning (15610): No output dependent on input pin \"SW\[16\]\"" {  } { { "UnsignMulti.v" "" { Text "D:/PROGRAMING/fpga/UnsignMulti/UnsignMulti.v" 6 -1 0 } }  } 0 15610 "No output dependent on input pin \"%1!s!\"" 0 0 "" 0} { "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN" "KEY\[1\] " "Warning (15610): No output dependent on input pin \"KEY\[1\]\"" {  } { { "UnsignMulti.v" "" { Text "D:/PROGRAMING/fpga/UnsignMulti/UnsignMulti.v" 7 -1 0 } }  } 0 15610 "No output dependent on input pin \"%1!s!\"" 0 0 "" 0} { "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN" "KEY\[2\] " "Warning (15610): No output dependent on input pin \"KEY\[2\]\"" {  } { { "UnsignMulti.v" "" { Text "D:/PROGRAMING/fpga/UnsignMulti/UnsignMulti.v" 7 -1 0 } }  } 0 15610 "No output dependent on input pin \"%1!s!\"" 0 0 "" 0} { "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN" "KEY\[3\] " "Warning (15610): No output dependent on input pin \"KEY\[3\]\"" {  } { { "UnsignMulti.v" "" { Text "D:/PROGRAMING/fpga/UnsignMulti/UnsignMulti.v" 7 -1 0 } }  } 0 15610 "No output dependent on input pin \"%1!s!\"" 0 0 "" 0}  } {  } 0 0 "Design contains %1!d! input pin(s) that do not drive logic" 0 0 "" 0}
{ "Info" "ICUT_CUT_TM_SUMMARY" "344 " "Info: Implemented 344 device resources after synthesis - the final resource count might be different" { { "Info" "ICUT_CUT_TM_IPINS" "22 " "Info: Implemented 22 input pins" {  } {  } 0 0 "Implemented %1!d! input pins" 0 0 "" 0} { "Info" "ICUT_CUT_TM_OPINS" "83 " "Info: Implemented 83 output pins" {  } {  } 0 0 "Implemented %1!d! output pins" 0 0 "" 0} { "Info" "ICUT_CUT_TM_LCELLS" "238 " "Info: Implemented 238 logic cells" {  } {  } 0 0 "Implemented %1!d! logic cells" 0 0 "" 0} { "Info" "ICUT_CUT_TM_DSP_ELEM" "1 " "Info: Implemented 1 DSP elements" {  } {  } 0 0 "Implemented %1!d! DSP elements" 0 0 "" 0}  } {  } 0 0 "Implemented %1!d! device resources after synthesis - the final resource count might be different" 0 0 "" 0}
{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 52 s Quartus II " "Info: Quartus II Analysis & Synthesis was successful. 0 errors, 52 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "146 " "Info: Allocated 146 megabytes of memory during processing" {  } {  } 0 0 "Allocated %1!s! megabytes of memory during processing" 0 0 "" 0} { "Info" "IQEXE_END_BANNER_TIME" "Sun Jul 13 17:08:01 2008 " "Info: Processing ended: Sun Jul 13 17:08:01 2008" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "" 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:08 " "Info: Elapsed time: 00:00:08" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "" 0}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "" 0}