prev_cmp_unsignmulti.map.qmsg

ALTERA上DE2平台

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0 "" 0}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus II " "Info: Running Quartus II Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 7.2 Build 207 03/18/2008 Service Pack 3 SJ Full Version " "Info: Version 7.2 Build 207 03/18/2008 Service Pack 3 SJ Full Version" {  } {  } 0 0 "%1!s!" 0 0 "" 0} { "Info" "IQEXE_START_BANNER_TIME" "Sun Jul 13 17:07:53 2008 " "Info: Processing started: Sun Jul 13 17:07:53 2008" {  } {  } 0 0 "Processing started: %1!s!" 0 0 "" 0}  } {  } 4 0 "Running %2!s! %1!s!" 0 0 "" 0}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off UnsignMulti -c UnsignMulti " "Info: Command: quartus_map --read_settings_files=on --write_settings_files=off UnsignMulti -c UnsignMulti" {  } {  } 0 0 "Command: %1!s!" 0 0 "" 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "UnsignMulti.v 5 5 " "Info: Found 5 design units, including 5 entities, in source file UnsignMulti.v" { { "Info" "ISGN_ENTITY_NAME" "1 UnsignMulti " "Info: Found entity 1: UnsignMulti" {  } { { "UnsignMulti.v" "" { Text "D:/PROGRAMING/fpga/UnsignMulti/UnsignMulti.v" 1 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0} { "Info" "ISGN_ENTITY_NAME" "2 BinMulti " "Info: Found entity 2: BinMulti" {  } { { "UnsignMulti.v" "" { Text "D:/PROGRAMING/fpga/UnsignMulti/UnsignMulti.v" 39 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0} { "Info" "ISGN_ENTITY_NAME" "3 BinDis " "Info: Found entity 3: BinDis" {  } { { "UnsignMulti.v" "" { Text "D:/PROGRAMING/fpga/UnsignMulti/UnsignMulti.v" 51 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0} { "Info" "ISGN_ENTITY_NAME" "4 BinToDec " "Info: Found entity 4: BinToDec" {  } { { "UnsignMulti.v" "" { Text "D:/PROGRAMING/fpga/UnsignMulti/UnsignMulti.v" 68 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0} { "Info" "ISGN_ENTITY_NAME" "5 DecDis " "Info: Found entity 5: DecDis" {  } { { "UnsignMulti.v" "" { Text "D:/PROGRAMING/fpga/UnsignMulti/UnsignMulti.v" 79 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0}
{ "Info" "ISGN_START_ELABORATION_TOP" "UnsignMulti " "Info: Elaborating entity \"UnsignMulti\" for the top level hierarchy" {  } {  } 0 0 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0 "" 0}
{ "Warning" "WVRFX_L2_VDB_DRIVERLESS_OUTPUT_PORT" "LEDR\[17\] UnsignMulti.v(8) " "Warning (10034): Output port \"LEDR\[17\]\" at UnsignMulti.v(8) has no driver" {  } { { "UnsignMulti.v" "" { Text "D:/PROGRAMING/fpga/UnsignMulti/UnsignMulti.v" 8 0 0 } }  } 0 10034 "Output port \"%1!s!\" at %2!s! has no driver" 0 0 "" 0}
{ "Warning" "WVRFX_L2_VDB_DRIVERLESS_OUTPUT_PORT" "LEDR\[16\] UnsignMulti.v(8) " "Warning (10034): Output port \"LEDR\[16\]\" at UnsignMulti.v(8) has no driver" {  } { { "UnsignMulti.v" "" { Text "D:/PROGRAMING/fpga/UnsignMulti/UnsignMulti.v" 8 0 0 } }  } 0 10034 "Output port \"%1!s!\" at %2!s! has no driver" 0 0 "" 0}
{ "Warning" "WVRFX_L2_VDB_DRIVERLESS_OUTPUT_PORT" "LEDR\[15\] UnsignMulti.v(8) " "Warning (10034): Output port \"LEDR\[15\]\" at UnsignMulti.v(8) has no driver" {  } { { "UnsignMulti.v" "" { Text "D:/PROGRAMING/fpga/UnsignMulti/UnsignMulti.v" 8 0 0 } }  } 0 10034 "Output port \"%1!s!\" at %2!s! has no driver" 0 0 "" 0}
{ "Warning" "WVRFX_L2_VDB_DRIVERLESS_OUTPUT_PORT" "LEDR\[14\] UnsignMulti.v(8) " "Warning (10034): Output port \"LEDR\[14\]\" at UnsignMulti.v(8) has no driver" {  } { { "UnsignMulti.v" "" { Text "D:/PROGRAMING/fpga/UnsignMulti/UnsignMulti.v" 8 0 0 } }  } 0 10034 "Output port \"%1!s!\" at %2!s! has no driver" 0 0 "" 0}
{ "Warning" "WVRFX_L2_VDB_DRIVERLESS_OUTPUT_PORT" "LEDR\[9\] UnsignMulti.v(8) " "Warning (10034): Output port \"LEDR\[9\]\" at UnsignMulti.v(8) has no driver" {  } { { "UnsignMulti.v" "" { Text "D:/PROGRAMING/fpga/UnsignMulti/UnsignMulti.v" 8 0 0 } }  } 0 10034 "Output port \"%1!s!\" at %2!s! has no driver" 0 0 "" 0}
{ "Warning" "WVRFX_L2_VDB_DRIVERLESS_OUTPUT_PORT" "LEDR\[8\] UnsignMulti.v(8) " "Warning (10034): Output port \"LEDR\[8\]\" at UnsignMulti.v(8) has no driver" {  } { { "UnsignMulti.v" "" { Text "D:/PROGRAMING/fpga/UnsignMulti/UnsignMulti.v" 8 0 0 } }  } 0 10034 "Output port \"%1!s!\" at %2!s! has no driver" 0 0 "" 0}
{ "Warning" "WVRFX_L2_VDB_DRIVERLESS_OUTPUT_PORT" "LEDR\[7\] UnsignMulti.v(8) " "Warning (10034): Output port \"LEDR\[7\]\" at UnsignMulti.v(8) has no driver" {  } { { "UnsignMulti.v" "" { Text "D:/PROGRAMING/fpga/UnsignMulti/UnsignMulti.v" 8 0 0 } }  } 0 10034 "Output port \"%1!s!\" at %2!s! has no driver" 0 0 "" 0}
{ "Warning" "WVRFX_L2_VDB_DRIVERLESS_OUTPUT_PORT" "LEDR\[6\] UnsignMulti.v(8) " "Warning (10034): Output port \"LEDR\[6\]\" at UnsignMulti.v(8) has no driver" {  } { { "UnsignMulti.v" "" { Text "D:/PROGRAMING/fpga/UnsignMulti/UnsignMulti.v" 8 0 0 } }  } 0 10034 "Output port \"%1!s!\" at %2!s! has no driver" 0 0 "" 0}
{ "Warning" "WVRFX_L2_VDB_DRIVERLESS_OUTPUT_PORT" "LEDR\[5\] UnsignMulti.v(8) " "Warning (10034): Output port \"LEDR\[5\]\" at UnsignMulti.v(8) has no driver" {  } { { "UnsignMulti.v" "" { Text "D:/PROGRAMING/fpga/UnsignMulti/UnsignMulti.v" 8 0 0 } }  } 0 10034 "Output port \"%1!s!\" at %2!s! has no driver" 0 0 "" 0}
{ "Warning" "WVRFX_L2_VDB_DRIVERLESS_OUTPUT_PORT" "LEDR\[4\] UnsignMulti.v(8) " "Warning (10034): Output port \"LEDR\[4\]\" at UnsignMulti.v(8) has no driver" {  } { { "UnsignMulti.v" "" { Text "D:/PROGRAMING/fpga/UnsignMulti/UnsignMulti.v" 8 0 0 } }  } 0 10034 "Output port \"%1!s!\" at %2!s! has no driver" 0 0 "" 0}
{ "Warning" "WVRFX_L2_VDB_DRIVERLESS_OUTPUT_PORT" "LEDG\[8\] UnsignMulti.v(9) " "Warning (10034): Output port \"LEDG\[8\]\" at UnsignMulti.v(9) has no driver" {  } { { "UnsignMulti.v" "" { Text "D:/PROGRAMING/fpga/UnsignMulti/UnsignMulti.v" 9 0 0 } }  } 0 10034 "Output port \"%1!s!\" at %2!s! has no driver" 0 0 "" 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "BinMulti BinMulti:BM1 " "Info: Elaborating entity \"BinMulti\" for hierarchy \"BinMulti:BM1\"" {  } { { "UnsignMulti.v" "BM1" { Text "D:/PROGRAMING/fpga/UnsignMulti/UnsignMulti.v" 19 0 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "BinToDec BinToDec:BTD1 " "Info: Elaborating entity \"BinToDec\" for hierarchy \"BinToDec:BTD1\"" {  } { { "UnsignMulti.v" "BTD1" { Text "D:/PROGRAMING/fpga/UnsignMulti/UnsignMulti.v" 20 0 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "8 4 UnsignMulti.v(75) " "Warning (10230): Verilog HDL assignment warning at UnsignMulti.v(75): truncated value with size 8 to match size of target (4)" {  } { { "UnsignMulti.v" "" { Text "D:/PROGRAMING/fpga/UnsignMulti/UnsignMulti.v" 75 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "" 0}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "8 4 UnsignMulti.v(76) " "Warning (10230): Verilog HDL assignment warning at UnsignMulti.v(76): truncated value with size 8 to match size of target (4)" {  } { { "UnsignMulti.v" "" { Text "D:/PROGRAMING/fpga/UnsignMulti/UnsignMulti.v" 76 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "" 0}