prev_cmp_unsignmulti.qmsg

ALTERA上DE2平台

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0 "" 0}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Elaboration Quartus II " "Info: Running Quartus II Analysis & Elaboration" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 7.2 Build 207 03/18/2008 Service Pack 3 SJ Full Version " "Info: Version 7.2 Build 207 03/18/2008 Service Pack 3 SJ Full Version" {  } {  } 0 0 "%1!s!" 0 0 "" 0} { "Info" "IQEXE_START_BANNER_TIME" "Sun Jul 13 17:07:31 2008 " "Info: Processing started: Sun Jul 13 17:07:31 2008" {  } {  } 0 0 "Processing started: %1!s!" 0 0 "" 0}  } {  } 4 0 "Running %2!s! %1!s!" 0 0 "" 0}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off UnsignMulti -c UnsignMulti --analysis_and_elaboration " "Info: Command: quartus_map --read_settings_files=on --write_settings_files=off UnsignMulti -c UnsignMulti --analysis_and_elaboration" {  } {  } 0 0 "Command: %1!s!" 0 0 "" 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "UnsignMulti.v 5 5 " "Info: Found 5 design units, including 5 entities, in source file UnsignMulti.v" { { "Info" "ISGN_ENTITY_NAME" "1 UnsignMulti " "Info: Found entity 1: UnsignMulti" {  } { { "UnsignMulti.v" "" { Text "D:/PROGRAMING/fpga/UnsignMulti/UnsignMulti.v" 1 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0} { "Info" "ISGN_ENTITY_NAME" "2 BinMulti " "Info: Found entity 2: BinMulti" {  } { { "UnsignMulti.v" "" { Text "D:/PROGRAMING/fpga/UnsignMulti/UnsignMulti.v" 39 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0} { "Info" "ISGN_ENTITY_NAME" "3 BinDis " "Info: Found entity 3: BinDis" {  } { { "UnsignMulti.v" "" { Text "D:/PROGRAMING/fpga/UnsignMulti/UnsignMulti.v" 51 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0} { "Info" "ISGN_ENTITY_NAME" "4 BinToDec " "Info: Found entity 4: BinToDec" {  } { { "UnsignMulti.v" "" { Text "D:/PROGRAMING/fpga/UnsignMulti/UnsignMulti.v" 68 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0} { "Info" "ISGN_ENTITY_NAME" "5 DecDis " "Info: Found entity 5: DecDis" {  } { { "UnsignMulti.v" "" { Text "D:/PROGRAMING/fpga/UnsignMulti/UnsignMulti.v" 79 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0}
{ "Info" "ISGN_START_ELABORATION_TOP" "UnsignMulti " "Info: Elaborating entity \"UnsignMulti\" for the top level hierarchy" {  } {  } 0 0 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0 "" 0}
{ "Warning" "WVRFX_L2_VDB_DRIVERLESS_OUTPUT_PORT" "LEDR\[17\] UnsignMulti.v(8) " "Warning (10034): Output port \"LEDR\[17\]\" at UnsignMulti.v(8) has no driver" {  } { { "UnsignMulti.v" "" { Text "D:/PROGRAMING/fpga/UnsignMulti/UnsignMulti.v" 8 0 0 } }  } 0 10034 "Output port \"%1!s!\" at %2!s! has no driver" 0 0 "" 0}
{ "Warning" "WVRFX_L2_VDB_DRIVERLESS_OUTPUT_PORT" "LEDR\[16\] UnsignMulti.v(8) " "Warning (10034): Output port \"LEDR\[16\]\" at UnsignMulti.v(8) has no driver" {  } { { "UnsignMulti.v" "" { Text "D:/PROGRAMING/fpga/UnsignMulti/UnsignMulti.v" 8 0 0 } }  } 0 10034 "Output port \"%1!s!\" at %2!s! has no driver" 0 0 "" 0}
{ "Warning" "WVRFX_L2_VDB_DRIVERLESS_OUTPUT_PORT" "LEDR\[15\] UnsignMulti.v(8) " "Warning (10034): Output port \"LEDR\[15\]\" at UnsignMulti.v(8) has no driver" {  } { { "UnsignMulti.v" "" { Text "D:/PROGRAMING/fpga/UnsignMulti/UnsignMulti.v" 8 0 0 } }  } 0 10034 "Output port \"%1!s!\" at %2!s! has no driver" 0 0 "" 0}
{ "Warning" "WVRFX_L2_VDB_DRIVERLESS_OUTPUT_PORT" "LEDR\[14\] UnsignMulti.v(8) " "Warning (10034): Output port \"LEDR\[14\]\" at UnsignMulti.v(8) has no driver" {  } { { "UnsignMulti.v" "" { Text "D:/PROGRAMING/fpga/UnsignMulti/UnsignMulti.v" 8 0 0 } }  } 0 10034 "Output port \"%1!s!\" at %2!s! has no driver" 0 0 "" 0}
{ "Warning" "WVRFX_L2_VDB_DRIVERLESS_OUTPUT_PORT" "LEDR\[9\] UnsignMulti.v(8) " "Warning (10034): Output port \"LEDR\[9\]\" at UnsignMulti.v(8) has no driver" {  } { { "UnsignMulti.v" "" { Text "D:/PROGRAMING/fpga/UnsignMulti/UnsignMulti.v" 8 0 0 } }  } 0 10034 "Output port \"%1!s!\" at %2!s! has no driver" 0 0 "" 0}
{ "Warning" "WVRFX_L2_VDB_DRIVERLESS_OUTPUT_PORT" "LEDR\[8\] UnsignMulti.v(8) " "Warning (10034): Output port \"LEDR\[8\]\" at UnsignMulti.v(8) has no driver" {  } { { "UnsignMulti.v" "" { Text "D:/PROGRAMING/fpga/UnsignMulti/UnsignMulti.v" 8 0 0 } }  } 0 10034 "Output port \"%1!s!\" at %2!s! has no driver" 0 0 "" 0}
{ "Warning" "WVRFX_L2_VDB_DRIVERLESS_OUTPUT_PORT" "LEDR\[7\] UnsignMulti.v(8) " "Warning (10034): Output port \"LEDR\[7\]\" at UnsignMulti.v(8) has no driver" {  } { { "UnsignMulti.v" "" { Text "D:/PROGRAMING/fpga/UnsignMulti/UnsignMulti.v" 8 0 0 } }  } 0 10034 "Output port \"%1!s!\" at %2!s! has no driver" 0 0 "" 0}
{ "Warning" "WVRFX_L2_VDB_DRIVERLESS_OUTPUT_PORT" "LEDR\[6\] UnsignMulti.v(8) " "Warning (10034): Output port \"LEDR\[6\]\" at UnsignMulti.v(8) has no driver" {  } { { "UnsignMulti.v" "" { Text "D:/PROGRAMING/fpga/UnsignMulti/UnsignMulti.v" 8 0 0 } }  } 0 10034 "Output port \"%1!s!\" at %2!s! has no driver" 0 0 "" 0}
{ "Warning" "WVRFX_L2_VDB_DRIVERLESS_OUTPUT_PORT" "LEDR\[5\] UnsignMulti.v(8) " "Warning (10034): Output port \"LEDR\[5\]\" at UnsignMulti.v(8) has no driver" {  } { { "UnsignMulti.v" "" { Text "D:/PROGRAMING/fpga/UnsignMulti/UnsignMulti.v" 8 0 0 } }  } 0 10034 "Output port \"%1!s!\" at %2!s! has no driver" 0 0 "" 0}
{ "Warning" "WVRFX_L2_VDB_DRIVERLESS_OUTPUT_PORT" "LEDR\[4\] UnsignMulti.v(8) " "Warning (10034): Output port \"LEDR\[4\]\" at UnsignMulti.v(8) has no driver" {  } { { "UnsignMulti.v" "" { Text "D:/PROGRAMING/fpga/UnsignMulti/UnsignMulti.v" 8 0 0 } }  } 0 10034 "Output port \"%1!s!\" at %2!s! has no driver" 0 0 "" 0}
{ "Warning" "WVRFX_L2_VDB_DRIVERLESS_OUTPUT_PORT" "LEDG\[8\] UnsignMulti.v(9) " "Warning (10034): Output port \"LEDG\[8\]\" at UnsignMulti.v(9) has no driver" {  } { { "UnsignMulti.v" "" { Text "D:/PROGRAMING/fpga/UnsignMulti/UnsignMulti.v" 9 0 0 } }  } 0 10034 "Output port \"%1!s!\" at %2!s! has no driver" 0 0 "" 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "BinMulti BinMulti:BM1 " "Info: Elaborating entity \"BinMulti\" for hierarchy \"BinMulti:BM1\"" {  } { { "UnsignMulti.v" "BM1" { Text "D:/PROGRAMING/fpga/UnsignMulti/UnsignMulti.v" 19 0 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "BinToDec BinToDec:BTD1 " "Info: Elaborating entity \"BinToDec\" for hierarchy \"BinToDec:BTD1\"" {  } { { "UnsignMulti.v" "BTD1" { Text "D:/PROGRAMING/fpga/UnsignMulti/UnsignMulti.v" 20 0 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "8 4 UnsignMulti.v(75) " "Warning (10230): Verilog HDL assignment warning at UnsignMulti.v(75): truncated value with size 8 to match size of target (4)" {  } { { "UnsignMulti.v" "" { Text "D:/PROGRAMING/fpga/UnsignMulti/UnsignMulti.v" 75 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "" 0}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "8 4 UnsignMulti.v(76) " "Warning (10230): Verilog HDL assignment warning at UnsignMulti.v(76): truncated value with size 8 to match size of target (4)" {  } { { "UnsignMulti.v" "" { Text "D:/PROGRAMING/fpga/UnsignMulti/UnsignMulti.v" 76 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "" 0}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "8 4 UnsignMulti.v(77) " "Warning (10230): Verilog HDL assignment warning at UnsignMulti.v(77): truncated value with size 8 to match size of target (4)" {  } { { "UnsignMulti.v" "" { Text "D:/PROGRAMING/fpga/UnsignMulti/UnsignMulti.v" 77 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "" 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "BinDis BinDis:BD1 " "Info: Elaborating entity \"BinDis\" for hierarchy \"BinDis:BD1\"" {  } { { "UnsignMulti.v" "BD1" { Text "D:/PROGRAMING/fpga/UnsignMulti/UnsignMulti.v" 23 0 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "BinDis BinDis:BD3 " "Info: Elaborating entity \"BinDis\" for hierarchy \"BinDis:BD3\"" {  } { { "UnsignMulti.v" "BD3" { Text "D:/PROGRAMING/fpga/UnsignMulti/UnsignMulti.v" 25 0 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "DecDis DecDis:DD2 " "Info: Elaborating entity \"DecDis\" for hierarchy \"DecDis:DD2\"" {  } { { "UnsignMulti.v" "DD2" { Text "D:/PROGRAMING/fpga/UnsignMulti/UnsignMulti.v" 27 0 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0}
{ "Warning" "WSGN_WIDTH_MISMATCH_INPUT_PORT_TOO_WIDE" "ordered port 0 BTD2 4 8 " "Warning (12010): Port \"ordered port 0\" on the entity instantiation of \"BTD2\" is connected to a signal of width 4. The formal width of the signal in the module is 8.  Extra bits will be driven by GND." {  } { { "UnsignMulti.v" "BTD2" { Text "D:/PROGRAMING/fpga/UnsignMulti/UnsignMulti.v" 21 0 0 } }  } 0 12010 "Port \"%1!s!\" on the entity instantiation of \"%2!s!\" is connected to a signal of width %3!d!. The formal width of the signal in the module is %4!d!.  Extra bits will be driven by GND." 0 0 "" 0}
{ "Warning" "WSGN_WIDTH_MISMATCH_INPUT_PORT_TOO_WIDE" "ordered port 0 BTD1 4 8 " "Warning (12010): Port \"ordered port 0\" on the entity instantiation of \"BTD1\" is connected to a signal of width 4. The formal width of the signal in the module is 8.  Extra bits will be driven by GND." {  } { { "UnsignMulti.v" "BTD1" { Text "D:/PROGRAMING/fpga/UnsignMulti/UnsignMulti.v" 20 0 0 } }  } 0 12010 "Port \"%1!s!\" on the entity instantiation of \"%2!s!\" is connected to a signal of width %3!d!. The formal width of the signal in the module is %4!d!.  Extra bits will be driven by GND." 0 0 "" 0}
{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Elaboration 0 s 16 s Quartus II " "Info: Quartus II Analysis & Elaboration was successful. 0 errors, 16 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "137 " "Info: Allocated 137 megabytes of memory during processing" {  } {  } 0 0 "Allocated %1!s! megabytes of memory during processing" 0 0 "" 0} { "Info" "IQEXE_END_BANNER_TIME" "Sun Jul 13 17:07:33 2008 " "Info: Processing ended: Sun Jul 13 17:07:33 2008" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "" 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:02 " "Info: Elapsed time: 00:00:02" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "" 0}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "" 0}