lcd.tan.rpt

ALTERA上DE2平台

; N/A   ; None         ; 6.373 ns   ; data[4] ; LCD_DATA[4] ; CLOCK_50   ;
; N/A   ; None         ; 6.371 ns   ; data[3] ; LCD_DATA[3] ; CLOCK_50   ;
; N/A   ; None         ; 6.367 ns   ; data[5] ; LCD_DATA[5] ; CLOCK_50   ;
; N/A   ; None         ; 6.362 ns   ; data[0] ; LCD_DATA[0] ; CLOCK_50   ;
; N/A   ; None         ; 6.060 ns   ; data[8] ; LCD_RS      ; CLOCK_50   ;
+-------+--------------+------------+---------+-------------+------------+


+--------------------------+
; Timing Analyzer Messages ;
+--------------------------+
Info: *******************************************************************
Info: Running Quartus II Classic Timing Analyzer
    Info: Version 7.2 Build 207 03/18/2008 Service Pack 3 SJ Full Version
    Info: Processing started: Sun Jul 27 11:35:51 2008
Info: Command: quartus_tan --read_settings_files=off --write_settings_files=off LCD -c LCD --timing_analysis_only
Warning: Found pins functioning as undefined clocks and/or memory enables
    Info: Assuming node "CLOCK_50" is an undefined clock
Warning: Found 9 node(s) in clock paths which may be acting as ripple and/or gated clocks -- node(s) analyzed as buffer(s) resulting in clock skew
    Info: Detected ripple clock "State[5]" as buffer
    Info: Detected ripple clock "State[3]" as buffer
    Info: Detected ripple clock "State[0]" as buffer
    Info: Detected ripple clock "State[1]" as buffer
    Info: Detected ripple clock "State[2]" as buffer
    Info: Detected ripple clock "State[4]" as buffer
    Info: Detected gated clock "LessThan1~69" as buffer
    Info: Detected gated clock "Decoder2~88" as buffer
    Info: Detected gated clock "always1~0" as buffer
Info: Clock "CLOCK_50" has Internal fmax of 144.78 MHz between source register "CountEnd[0]" and destination register "Count[9]" (period= 6.907 ns)
    Info: + Longest register to register delay is 4.383 ns
        Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LCFF_X23_Y20_N25; Fanout = 15; REG Node = 'CountEnd[0]'
        Info: 2: + IC(0.526 ns) + CELL(0.150 ns) = 0.676 ns; Loc. = LCCOMB_X23_Y20_N26; Fanout = 3; COMB Node = 'LessThan0~1942'
        Info: 3: + IC(0.951 ns) + CELL(0.150 ns) = 1.777 ns; Loc. = LCCOMB_X23_Y21_N10; Fanout = 1; COMB Node = 'LessThan0~1946'
        Info: 4: + IC(0.720 ns) + CELL(0.150 ns) = 2.647 ns; Loc. = LCCOMB_X23_Y20_N20; Fanout = 1; COMB Node = 'LessThan0~1950'
        Info: 5: + IC(0.252 ns) + CELL(0.275 ns) = 3.174 ns; Loc. = LCCOMB_X23_Y20_N28; Fanout = 20; COMB Node = 'LessThan0~1957'
        Info: 6: + IC(0.699 ns) + CELL(0.510 ns) = 4.383 ns; Loc. = LCFF_X23_Y21_N31; Fanout = 4; REG Node = 'Count[9]'
        Info: Total cell delay = 1.235 ns ( 28.18 % )
        Info: Total interconnect delay = 3.148 ns ( 71.82 % )
    Info: - Smallest clock skew is -2.310 ns
        Info: + Shortest clock path from clock "CLOCK_50" to destination register is 2.687 ns
            Info: 1: + IC(0.000 ns) + CELL(0.999 ns) = 0.999 ns; Loc. = PIN_N2; Fanout = 2; CLK Node = 'CLOCK_50'
            Info: 2: + IC(0.118 ns) + CELL(0.000 ns) = 1.117 ns; Loc. = CLKCTRL_G2; Fanout = 29; COMB Node = 'CLOCK_50~clkctrl'
            Info: 3: + IC(1.033 ns) + CELL(0.537 ns) = 2.687 ns; Loc. = LCFF_X23_Y21_N31; Fanout = 4; REG Node = 'Count[9]'
            Info: Total cell delay = 1.536 ns ( 57.16 % )
            Info: Total interconnect delay = 1.151 ns ( 42.84 % )
        Info: - Longest clock path from clock "CLOCK_50" to source register is 4.997 ns
            Info: 1: + IC(0.000 ns) + CELL(0.999 ns) = 0.999 ns; Loc. = PIN_N2; Fanout = 2; CLK Node = 'CLOCK_50'
            Info: 2: + IC(1.153 ns) + CELL(0.150 ns) = 2.302 ns; Loc. = LCCOMB_X1_Y25_N10; Fanout = 1; COMB Node = 'always1~0'
            Info: 3: + IC(1.124 ns) + CELL(0.000 ns) = 3.426 ns; Loc. = CLKCTRL_G3; Fanout = 13; COMB Node = 'always1~0clkctrl'
            Info: 4: + IC(1.034 ns) + CELL(0.537 ns) = 4.997 ns; Loc. = LCFF_X23_Y20_N25; Fanout = 15; REG Node = 'CountEnd[0]'
            Info: Total cell delay = 1.686 ns ( 33.74 % )
            Info: Total interconnect delay = 3.311 ns ( 66.26 % )
    Info: + Micro clock to output delay of source is 0.250 ns
    Info: + Micro setup delay of destination is -0.036 ns
Info: tco from clock "CLOCK_50" to destination pin "LCD_EN" through register "en" is 10.276 ns
    Info: + Longest clock path from clock "CLOCK_50" to source register is 4.996 ns
        Info: 1: + IC(0.000 ns) + CELL(0.999 ns) = 0.999 ns; Loc. = PIN_N2; Fanout = 2; CLK Node = 'CLOCK_50'
        Info: 2: + IC(1.153 ns) + CELL(0.150 ns) = 2.302 ns; Loc. = LCCOMB_X1_Y25_N10; Fanout = 1; COMB Node = 'always1~0'
        Info: 3: + IC(1.124 ns) + CELL(0.000 ns) = 3.426 ns; Loc. = CLKCTRL_G3; Fanout = 13; COMB Node = 'always1~0clkctrl'
        Info: 4: + IC(1.033 ns) + CELL(0.537 ns) = 4.996 ns; Loc. = LCFF_X22_Y20_N7; Fanout = 2; REG Node = 'en'
        Info: Total cell delay = 1.686 ns ( 33.75 % )
        Info: Total interconnect delay = 3.310 ns ( 66.25 % )
    Info: + Micro clock to output delay of source is 0.250 ns
    Info: + Longest register to pin delay is 5.030 ns
        Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LCFF_X22_Y20_N7; Fanout = 2; REG Node = 'en'
        Info: 2: + IC(2.398 ns) + CELL(2.632 ns) = 5.030 ns; Loc. = PIN_K3; Fanout = 0; PIN Node = 'LCD_EN'
        Info: Total cell delay = 2.632 ns ( 52.33 % )
        Info: Total interconnect delay = 2.398 ns ( 47.67 % )
Info: Quartus II Classic Timing Analyzer was successful. 0 errors, 2 warnings
    Info: Allocated 116 megabytes of memory during processing
    Info: Processing ended: Sun Jul 27 11:35:52 2008
    Info: Elapsed time: 00:00:01