lcd.map.qmsg

ALTERA上DE2平台

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0 "" 0}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus II " "Info: Running Quartus II Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 7.2 Build 207 03/18/2008 Service Pack 3 SJ Full Version " "Info: Version 7.2 Build 207 03/18/2008 Service Pack 3 SJ Full Version" {  } {  } 0 0 "%1!s!" 0 0 "" 0} { "Info" "IQEXE_START_BANNER_TIME" "Sun Jul 27 11:35:00 2008 " "Info: Processing started: Sun Jul 27 11:35:00 2008" {  } {  } 0 0 "Processing started: %1!s!" 0 0 "" 0}  } {  } 4 0 "Running %2!s! %1!s!" 0 0 "" 0}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off LCD -c LCD " "Info: Command: quartus_map --read_settings_files=on --write_settings_files=off LCD -c LCD" {  } {  } 0 0 "Command: %1!s!" 0 0 "" 0}
{ "Warning" "WVRFX_VERI_COMPLICATED_EVENT_EXPR" "LCD.v(63) " "Warning (10261): Verilog HDL Event Control warning at LCD.v(63): Event Control contains a complex event expression" {  } { { "LCD.v" "" { Text "D:/PROGRAMING/fpga/LCD/LCD.v" 63 0 0 } }  } 0 10261 "Verilog HDL Event Control warning at %1!s!: Event Control contains a complex event expression" 0 0 "" 0}
{ "Warning" "WSGN_SEARCH_FILE" "LCD.v 1 1 " "Warning: Using design file LCD.v, which is not specified as a design file for the current project, but contains definitions for 1 design units and 1 entities in project" { { "Info" "ISGN_ENTITY_NAME" "1 LCD " "Info: Found entity 1: LCD" {  } { { "LCD.v" "" { Text "D:/PROGRAMING/fpga/LCD/LCD.v" 1 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0}  } {  } 0 0 "Using design file %1!s!, which is not specified as a design file for the current project, but contains definitions for %2!llu! design units and %3!llu! entities in project" 0 0 "" 0}
{ "Info" "ISGN_START_ELABORATION_TOP" "LCD " "Info: Elaborating entity \"LCD\" for the top level hierarchy" {  } {  } 0 0 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0 "" 0}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 6 LCD.v(73) " "Warning (10230): Verilog HDL assignment warning at LCD.v(73): truncated value with size 32 to match size of target (6)" {  } { { "LCD.v" "" { Text "D:/PROGRAMING/fpga/LCD/LCD.v" 73 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "" 0}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 3 LCD.v(74) " "Warning (10230): Verilog HDL assignment warning at LCD.v(74): truncated value with size 32 to match size of target (3)" {  } { { "LCD.v" "" { Text "D:/PROGRAMING/fpga/LCD/LCD.v" 74 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "" 0}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 3 LCD.v(77) " "Warning (10230): Verilog HDL assignment warning at LCD.v(77): truncated value with size 32 to match size of target (3)" {  } { { "LCD.v" "" { Text "D:/PROGRAMING/fpga/LCD/LCD.v" 77 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "" 0}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 3 LCD.v(85) " "Warning (10230): Verilog HDL assignment warning at LCD.v(85): truncated value with size 32 to match size of target (3)" {  } { { "LCD.v" "" { Text "D:/PROGRAMING/fpga/LCD/LCD.v" 85 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "" 0}
{ "Warning" "WVRFX_L2_VDB_DRIVERLESS_OUTPUT_PORT" "LEDR\[17\] LCD.v(14) " "Warning (10034): Output port \"LEDR\[17\]\" at LCD.v(14) has no driver" {  } { { "LCD.v" "" { Text "D:/PROGRAMING/fpga/LCD/LCD.v" 14 0 0 } }  } 0 10034 "Output port \"%1!s!\" at %2!s! has no driver" 0 0 "" 0}
{ "Warning" "WVRFX_L2_VDB_DRIVERLESS_OUTPUT_PORT" "LEDR\[16\] LCD.v(14) " "Warning (10034): Output port \"LEDR\[16\]\" at LCD.v(14) has no driver" {  } { { "LCD.v" "" { Text "D:/PROGRAMING/fpga/LCD/LCD.v" 14 0 0 } }  } 0 10034 "Output port \"%1!s!\" at %2!s! has no driver" 0 0 "" 0}
{ "Warning" "WVRFX_L2_VDB_DRIVERLESS_OUTPUT_PORT" "LEDR\[15\] LCD.v(14) " "Warning (10034): Output port \"LEDR\[15\]\" at LCD.v(14) has no driver" {  } { { "LCD.v" "" { Text "D:/PROGRAMING/fpga/LCD/LCD.v" 14 0 0 } }  } 0 10034 "Output port \"%1!s!\" at %2!s! has no driver" 0 0 "" 0}
{ "Warning" "WVRFX_L2_VDB_DRIVERLESS_OUTPUT_PORT" "LEDR\[14\] LCD.v(14) " "Warning (10034): Output port \"LEDR\[14\]\" at LCD.v(14) has no driver" {  } { { "LCD.v" "" { Text "D:/PROGRAMING/fpga/LCD/LCD.v" 14 0 0 } }  } 0 10034 "Output port \"%1!s!\" at %2!s! has no driver" 0 0 "" 0}
{ "Warning" "WVRFX_L2_VDB_DRIVERLESS_OUTPUT_PORT" "LEDR\[13\] LCD.v(14) " "Warning (10034): Output port \"LEDR\[13\]\" at LCD.v(14) has no driver" {  } { { "LCD.v" "" { Text "D:/PROGRAMING/fpga/LCD/LCD.v" 14 0 0 } }  } 0 10034 "Output port \"%1!s!\" at %2!s! has no driver" 0 0 "" 0}
{ "Warning" "WVRFX_L2_VDB_DRIVERLESS_OUTPUT_PORT" "LEDR\[12\] LCD.v(14) " "Warning (10034): Output port \"LEDR\[12\]\" at LCD.v(14) has no driver" {  } { { "LCD.v" "" { Text "D:/PROGRAMING/fpga/LCD/LCD.v" 14 0 0 } }  } 0 10034 "Output port \"%1!s!\" at %2!s! has no driver" 0 0 "" 0}
{ "Warning" "WVRFX_L2_VDB_DRIVERLESS_OUTPUT_PORT" "LEDR\[11\] LCD.v(14) " "Warning (10034): Output port \"LEDR\[11\]\" at LCD.v(14) has no driver" {  } { { "LCD.v" "" { Text "D:/PROGRAMING/fpga/LCD/LCD.v" 14 0 0 } }  } 0 10034 "Output port \"%1!s!\" at %2!s! has no driver" 0 0 "" 0}
{ "Warning" "WVRFX_L2_VDB_DRIVERLESS_OUTPUT_PORT" "LEDR\[10\] LCD.v(14) " "Warning (10034): Output port \"LEDR\[10\]\" at LCD.v(14) has no driver" {  } { { "LCD.v" "" { Text "D:/PROGRAMING/fpga/LCD/LCD.v" 14 0 0 } }  } 0 10034 "Output port \"%1!s!\" at %2!s! has no driver" 0 0 "" 0}