prev_cmp_lcd.tan.qmsg

ALTERA上DE2平台

{ "Info" "ITDB_FULL_CLOCK_REG_RESULT" "CLOCK_50 register CountEnd\[0\] register Count\[9\] 144.78 MHz 6.907 ns Internal " "Info: Clock \"CLOCK_50\" has Internal fmax of 144.78 MHz between source register \"CountEnd\[0\]\" and destination register \"Count\[9\]\" (period= 6.907 ns)" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "4.383 ns + Longest register register " "Info: + Longest register to register delay is 4.383 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns CountEnd\[0\] 1 REG LCFF_X23_Y20_N25 15 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LCFF_X23_Y20_N25; Fanout = 15; REG Node = 'CountEnd\[0\]'" {  } { { "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { CountEnd[0] } "NODE_NAME" } } { "LCD.v" "" { Text "D:/PROGRAMING/fpga/LCD/LCD.v" 63 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.526 ns) + CELL(0.150 ns) 0.676 ns LessThan0~1942 2 COMB LCCOMB_X23_Y20_N26 3 " "Info: 2: + IC(0.526 ns) + CELL(0.150 ns) = 0.676 ns; Loc. = LCCOMB_X23_Y20_N26; Fanout = 3; COMB Node = 'LessThan0~1942'" {  } { { "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.676 ns" { CountEnd[0] LessThan0~1942 } "NODE_NAME" } } { "LCD.v" "" { Text "D:/PROGRAMING/fpga/LCD/LCD.v" 54 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.951 ns) + CELL(0.150 ns) 1.777 ns LessThan0~1946 3 COMB LCCOMB_X23_Y21_N10 1 " "Info: 3: + IC(0.951 ns) + CELL(0.150 ns) = 1.777 ns; Loc. = LCCOMB_X23_Y21_N10; Fanout = 1; COMB Node = 'LessThan0~1946'" {  } { { "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "1.101 ns" { LessThan0~1942 LessThan0~1946 } "NODE_NAME" } } { "LCD.v" "" { Text "D:/PROGRAMING/fpga/LCD/LCD.v" 54 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.720 ns) + CELL(0.150 ns) 2.647 ns LessThan0~1950 4 COMB LCCOMB_X23_Y20_N20 1 " "Info: 4: + IC(0.720 ns) + CELL(0.150 ns) = 2.647 ns; Loc. = LCCOMB_X23_Y20_N20; Fanout = 1; COMB Node = 'LessThan0~1950'" {  } { { "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.870 ns" { LessThan0~1946 LessThan0~1950 } "NODE_NAME" } } { "LCD.v" "" { Text "D:/PROGRAMING/fpga/LCD/LCD.v" 54 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.252 ns) + CELL(0.275 ns) 3.174 ns LessThan0~1957 5 COMB LCCOMB_X23_Y20_N28 20 " "Info: 5: + IC(0.252 ns) + CELL(0.275 ns) = 3.174 ns; Loc. = LCCOMB_X23_Y20_N28; Fanout = 20; COMB Node = 'LessThan0~1957'" {  } { { "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.527 ns" { LessThan0~1950 LessThan0~1957 } "NODE_NAME" } } { "LCD.v" "" { Text "D:/PROGRAMING/fpga/LCD/LCD.v" 54 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.699 ns) + CELL(0.510 ns) 4.383 ns Count\[9\] 6 REG LCFF_X23_Y21_N31 4 " "Info: 6: + IC(0.699 ns) + CELL(0.510 ns) = 4.383 ns; Loc. = LCFF_X23_Y21_N31; Fanout = 4; REG Node = 'Count\[9\]'" {  } { { "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "1.209 ns" { LessThan0~1957 Count[9] } "NODE_NAME" } } { "LCD.v" "" { Text "D:/PROGRAMING/fpga/LCD/LCD.v" 50 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.235 ns ( 28.18 % ) " "Info: Total cell delay = 1.235 ns ( 28.18 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "3.148 ns ( 71.82 % ) " "Info: Total interconnect delay = 3.148 ns ( 71.82 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "4.383 ns" { CountEnd[0] LessThan0~1942 LessThan0~1946 LessThan0~1950 LessThan0~1957 Count[9] } "NODE_NAME" } } { "e:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "e:/altera/72/quartus/bin/Technology_Viewer.qrui" "4.383 ns" { CountEnd[0] {} LessThan0~1942 {} LessThan0~1946 {} LessThan0~1950 {} LessThan0~1957 {} Count[9] {} } { 0.000ns 0.526ns 0.951ns 0.720ns 0.252ns 0.699ns } { 0.000ns 0.150ns 0.150ns 0.150ns 0.275ns 0.510ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "-2.310 ns - Smallest " "Info: - Smallest clock skew is -2.310 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "CLOCK_50 destination 2.687 ns + Shortest register " "Info: + Shortest clock path from clock \"CLOCK_50\" to destination register is 2.687 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.999 ns) 0.999 ns CLOCK_50 1 CLK PIN_N2 2 " "Info: 1: + IC(0.000 ns) + CELL(0.999 ns) = 0.999 ns; Loc. = PIN_N2; Fanout = 2; CLK Node = 'CLOCK_50'" {  } { { "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { CLOCK_50 } "NODE_NAME" } } { "LCD.v" "" { Text "D:/PROGRAMING/fpga/LCD/LCD.v" 12 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.118 ns) + CELL(0.000 ns) 1.117 ns CLOCK_50~clkctrl 2 COMB CLKCTRL_G2 29 " "Info: 2: + IC(0.118 ns) + CELL(0.000 ns) = 1.117 ns; Loc. = CLKCTRL_G2; Fanout = 29; COMB Node = 'CLOCK_50~clkctrl'" {  } { { "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.118 ns" { CLOCK_50 CLOCK_50~clkctrl } "NODE_NAME" } } { "LCD.v" "" { Text "D:/PROGRAMING/fpga/LCD/LCD.v" 12 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.033 ns) + CELL(0.537 ns) 2.687 ns Count\[9\] 3 REG LCFF_X23_Y21_N31 4 " "Info: 3: + IC(1.033 ns) + CELL(0.537 ns) = 2.687 ns; Loc. = LCFF_X23_Y21_N31; Fanout = 4; REG Node = 'Count\[9\]'" {  } { { "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "1.570 ns" { CLOCK_50~clkctrl Count[9] } "NODE_NAME" } } { "LCD.v" "" { Text "D:/PROGRAMING/fpga/LCD/LCD.v" 50 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.536 ns ( 57.16 % ) " "Info: Total cell delay = 1.536 ns ( 57.16 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.151 ns ( 42.84 % ) " "Info: Total interconnect delay = 1.151 ns ( 42.84 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.687 ns" { CLOCK_50 CLOCK_50~clkctrl Count[9] } "NODE_NAME" } } { "e:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "e:/altera/72/quartus/bin/Technology_Viewer.qrui" "2.687 ns" { CLOCK_50 {} CLOCK_50~combout {} CLOCK_50~clkctrl {} Count[9] {} } { 0.000ns 0.000ns 0.118ns 1.033ns } { 0.000ns 0.999ns 0.000ns 0.537ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "CLOCK_50 source 4.997 ns - Longest register " "Info: - Longest clock path from clock \"CLOCK_50\" to source register is 4.997 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.999 ns) 0.999 ns CLOCK_50 1 CLK PIN_N2 2 " "Info: 1: + IC(0.000 ns) + CELL(0.999 ns) = 0.999 ns; Loc. = PIN_N2; Fanout = 2; CLK Node = 'CLOCK_50'" {  } { { "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { CLOCK_50 } "NODE_NAME" } } { "LCD.v" "" { Text "D:/PROGRAMING/fpga/LCD/LCD.v" 12 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.153 ns) + CELL(0.150 ns) 2.302 ns always1~0 2 COMB LCCOMB_X1_Y25_N10 1 " "Info: 2: + IC(1.153 ns) + CELL(0.150 ns) = 2.302 ns; Loc. = LCCOMB_X1_Y25_N10; Fanout = 1; COMB Node = 'always1~0'" {  } { { "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "1.303 ns" { CLOCK_50 always1~0 } "NODE_NAME" } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.124 ns) + CELL(0.000 ns) 3.426 ns always1~0clkctrl 3 COMB CLKCTRL_G3 13 " "Info: 3: + IC(1.124 ns) + CELL(0.000 ns) = 3.426 ns; Loc. = CLKCTRL_G3; Fanout = 13; COMB Node = 'always1~0clkctrl'" {  } { { "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "1.124 ns" { always1~0 always1~0clkctrl } "NODE_NAME" } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.034 ns) + CELL(0.537 ns) 4.997 ns CountEnd\[0\] 4 REG LCFF_X23_Y20_N25 15 " "Info: 4: + IC(1.034 ns) + CELL(0.537 ns) = 4.997 ns; Loc. = LCFF_X23_Y20_N25; Fanout = 15; REG Node = 'CountEnd\[0\]'" {  } { { "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "1.571 ns" { always1~0clkctrl CountEnd[0] } "NODE_NAME" } } { "LCD.v" "" { Text "D:/PROGRAMING/fpga/LCD/LCD.v" 63 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.686 ns ( 33.74 % ) " "Info: Total cell delay = 1.686 ns ( 33.74 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "3.311 ns ( 66.26 % ) " "Info: Total interconnect delay = 3.311 ns ( 66.26 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "4.997 ns" { CLOCK_50 always1~0 always1~0clkctrl CountEnd[0] } "NODE_NAME" } } { "e:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "e:/altera/72/quartus/bin/Technology_Viewer.qrui" "4.997 ns" { CLOCK_50 {} CLOCK_50~combout {} always1~0 {} always1~0clkctrl {} CountEnd[0] {} } { 0.000ns 0.000ns 1.153ns 1.124ns 1.034ns } { 0.000ns 0.999ns 0.150ns 0.000ns 0.537ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0}  } { { "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.687 ns" { CLOCK_50 CLOCK_50~clkctrl Count[9] } "NODE_NAME" } } { "e:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "e:/altera/72/quartus/bin/Technology_Viewer.qrui" "2.687 ns" { CLOCK_50 {} CLOCK_50~combout {} CLOCK_50~clkctrl {} Count[9] {} } { 0.000ns 0.000ns 0.118ns 1.033ns } { 0.000ns 0.999ns 0.000ns 0.537ns } "" } } { "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "4.997 ns" { CLOCK_50 always1~0 always1~0clkctrl CountEnd[0] } "NODE_NAME" } } { "e:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "e:/altera/72/quartus/bin/Technology_Viewer.qrui" "4.997 ns" { CLOCK_50 {} CLOCK_50~combout {} always1~0 {} always1~0clkctrl {} CountEnd[0] {} } { 0.000ns 0.000ns 1.153ns 1.124ns 1.034ns } { 0.000ns 0.999ns 0.150ns 0.000ns 0.537ns } "" } }  } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.250 ns + " "Info: + Micro clock to output delay of source is 0.250 ns" {  } { { "LCD.v" "" { Text "D:/PROGRAMING/fpga/LCD/LCD.v" 63 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TSU_DELAY" "-0.036 ns + " "Info: + Micro setup delay of destination is -0.036 ns" {  } { { "LCD.v" "" { Text "D:/PROGRAMING/fpga/LCD/LCD.v" 50 -1 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0 "" 0}  } { { "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "4.383 ns" { CountEnd[0] LessThan0~1942 LessThan0~1946 LessThan0~1950 LessThan0~1957 Count[9] } "NODE_NAME" } } { "e:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "e:/altera/72/quartus/bin/Technology_Viewer.qrui" "4.383 ns" { CountEnd[0] {} LessThan0~1942 {} LessThan0~1946 {} LessThan0~1950 {} LessThan0~1957 {} Count[9] {} } { 0.000ns 0.526ns 0.951ns 0.720ns 0.252ns 0.699ns } { 0.000ns 0.150ns 0.150ns 0.150ns 0.275ns 0.510ns } "" } } { "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.687 ns" { CLOCK_50 CLOCK_50~clkctrl Count[9] } "NODE_NAME" } } { "e:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "e:/altera/72/quartus/bin/Technology_Viewer.qrui" "2.687 ns" { CLOCK_50 {} CLOCK_50~combout {} CLOCK_50~clkctrl {} Count[9] {} } { 0.000ns 0.000ns 0.118ns 1.033ns } { 0.000ns 0.999ns 0.000ns 0.537ns } "" } } { "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "4.997 ns" { CLOCK_50 always1~0 always1~0clkctrl CountEnd[0] } "NODE_NAME" } } { "e:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "e:/altera/72/quartus/bin/Technology_Viewer.qrui" "4.997 ns" { CLOCK_50 {} CLOCK_50~combout {} always1~0 {} always1~0clkctrl {} CountEnd[0] {} } { 0.000ns 0.000ns 1.153ns 1.124ns 1.034ns } { 0.000ns 0.999ns 0.150ns 0.000ns 0.537ns } "" } }  } 0 0 "Clock \"%1!s!\" has %8!s! fmax of %6!s! between source %2!s! \"%3!s!\" and destination %4!s! \"%5!s!\" (period= %7!s!)" 0 0 "" 0}
{ "Info" "ITDB_FULL_TCO_RESULT" "CLOCK_50 LCD_EN en 10.276 ns register " "Info: tco from clock \"CLOCK_50\" to destination pin \"LCD_EN\" through register \"en\" is 10.276 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "CLOCK_50 source 4.996 ns + Longest register " "Info: + Longest clock path from clock \"CLOCK_50\" to source register is 4.996 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.999 ns) 0.999 ns CLOCK_50 1 CLK PIN_N2 2 " "Info: 1: + IC(0.000 ns) + CELL(0.999 ns) = 0.999 ns; Loc. = PIN_N2; Fanout = 2; CLK Node = 'CLOCK_50'" {  } { { "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { CLOCK_50 } "NODE_NAME" } } { "LCD.v" "" { Text "D:/PROGRAMING/fpga/LCD/LCD.v" 12 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.153 ns) + CELL(0.150 ns) 2.302 ns always1~0 2 COMB LCCOMB_X1_Y25_N10 1 " "Info: 2: + IC(1.153 ns) + CELL(0.150 ns) = 2.302 ns; Loc. = LCCOMB_X1_Y25_N10; Fanout = 1; COMB Node = 'always1~0'" {  } { { "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "1.303 ns" { CLOCK_50 always1~0 } "NODE_NAME" } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.124 ns) + CELL(0.000 ns) 3.426 ns always1~0clkctrl 3 COMB CLKCTRL_G3 13 " "Info: 3: + IC(1.124 ns) + CELL(0.000 ns) = 3.426 ns; Loc. = CLKCTRL_G3; Fanout = 13; COMB Node = 'always1~0clkctrl'" {  } { { "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "1.124 ns" { always1~0 always1~0clkctrl } "NODE_NAME" } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.033 ns) + CELL(0.537 ns) 4.996 ns en 4 REG LCFF_X22_Y20_N7 2 " "Info: 4: + IC(1.033 ns) + CELL(0.537 ns) = 4.996 ns; Loc. = LCFF_X22_Y20_N7; Fanout = 2; REG Node = 'en'" {  } { { "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "1.570 ns" { always1~0clkctrl en } "NODE_NAME" } } { "LCD.v" "" { Text "D:/PROGRAMING/fpga/LCD/LCD.v" 63 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.686 ns ( 33.75 % ) " "Info: Total cell delay = 1.686 ns ( 33.75 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "3.310 ns ( 66.25 % ) " "Info: Total interconnect delay = 3.310 ns ( 66.25 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "4.996 ns" { CLOCK_50 always1~0 always1~0clkctrl en } "NODE_NAME" } } { "e:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "e:/altera/72/quartus/bin/Technology_Viewer.qrui" "4.996 ns" { CLOCK_50 {} CLOCK_50~combout {} always1~0 {} always1~0clkctrl {} en {} } { 0.000ns 0.000ns 1.153ns 1.124ns 1.033ns } { 0.000ns 0.999ns 0.150ns 0.000ns 0.537ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.250 ns + " "Info: + Micro clock to output delay of source is 0.250 ns" {  } { { "LCD.v" "" { Text "D:/PROGRAMING/fpga/LCD/LCD.v" 63 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "5.030 ns + Longest register pin " "Info: + Longest register to pin delay is 5.030 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns en 1 REG LCFF_X22_Y20_N7 2 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LCFF_X22_Y20_N7; Fanout = 2; REG Node = 'en'" {  } { { "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { en } "NODE_NAME" } } { "LCD.v" "" { Text "D:/PROGRAMING/fpga/LCD/LCD.v" 63 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(2.398 ns) + CELL(2.632 ns) 5.030 ns LCD_EN 2 PIN PIN_K3 0 " "Info: 2: + IC(2.398 ns) + CELL(2.632 ns) = 5.030 ns; Loc. = PIN_K3; Fanout = 0; PIN Node = 'LCD_EN'" {  } { { "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "5.030 ns" { en LCD_EN } "NODE_NAME" } } { "LCD.v" "" { Text "D:/PROGRAMING/fpga/LCD/LCD.v" 16 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.632 ns ( 52.33 % ) " "Info: Total cell delay = 2.632 ns ( 52.33 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.398 ns ( 47.67 % ) " "Info: Total interconnect delay = 2.398 ns ( 47.67 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "5.030 ns" { en LCD_EN } "NODE_NAME" } } { "e:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "e:/altera/72/quartus/bin/Technology_Viewer.qrui" "5.030 ns" { en {} LCD_EN {} } { 0.000ns 2.398ns } { 0.000ns 2.632ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0}  } { { "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "4.996 ns" { CLOCK_50 always1~0 always1~0clkctrl en } "NODE_NAME" } } { "e:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "e:/altera/72/quartus/bin/Technology_Viewer.qrui" "4.996 ns" { CLOCK_50 {} CLOCK_50~combout {} always1~0 {} always1~0clkctrl {} en {} } { 0.000ns 0.000ns 1.153ns 1.124ns 1.033ns } { 0.000ns 0.999ns 0.150ns 0.000ns 0.537ns } "" } } { "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "5.030 ns" { en LCD_EN } "NODE_NAME" } } { "e:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "e:/altera/72/quartus/bin/Technology_Viewer.qrui" "5.030 ns" { en {} LCD_EN {} } { 0.000ns 2.398ns } { 0.000ns 2.632ns } "" } }  } 0 0 "tco from clock \"%1!s!\" to destination pin \"%2!s!\" through %5!s! \"%3!s!\" is %4!s!" 0 0 "" 0}
{ "Info" "IQEXE_ERROR_COUNT" "Classic Timing Analyzer 0 s 2 s Quartus II " "Info: Quartus II Classic Timing Analyzer was successful. 0 errors, 2 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "116 " "Info: Allocated 116 megabytes of memory during processing" {  } {  } 0 0 "Allocated %1!s! megabytes of memory during processing" 0 0 "" 0} { "Info" "IQEXE_END_BANNER_TIME" "Sun Jul 27 11:34:06 2008 " "Info: Processing ended: Sun Jul 27 11:34:06 2008" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "" 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:01 " "Info: Elapsed time: 00:00:01" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "" 0}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "" 0}