lcd_write_number_test.v
来自「ALTERA上DE2平台」· Verilog 代码 · 共 118 行
V
118 行
////////////////////////////////////////////////////////////////////////////////// Author: lsilvest//// Create Date: 02/03/2008//// Module Name: lcd_write_number_test//// Target Devices: Altera DE2//// Tool versions: Quartus II 7.2 Web Edition//// Description: This module tests the lcd_write_number module. It writes a counter// on the LCD display at each half second.//////////////////////////////////////////////////////////////////////////////////// Copyright (c) 2008 Authors//// Permission is hereby granted, free of charge, to any person obtaining a copy// of this software and associated documentation files (the "Software"), to deal// in the Software without restriction, including without limitation the rights// to use, copy, modify, merge, publish, distribute, sublicense, and/or sell// copies of the Software, and to permit persons to whom the Software is// furnished to do so, subject to the following conditions://// The above copyright notice and this permission notice shall be included in// all copies or substantial portions of the Software.//// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR// IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,// FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE// AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER// LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,// OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN// THE SOFTWARE.////////////////////////////////////////////////////////////////////////////////module lcd_write_number_test ( input CLOCK_50, output LCD_EN, output LCD_RW, output LCD_RS, output [7:0] LCD_DATA, output LCD_ON, output LCD_BLON ); wire if_ready; reg if_write; reg [31:0] if_data; reg [1:0] state; reg [31:0] cntr; parameter IDLE = 2'b00, IF_WRITE_1 = 2'b01, SET_IF_WRITE_0 = 2'b10, WAIT = 2'b11; // Instantiate the Unit Under Test (UUT) lcd_write_number uut ( .CLOCK_50(CLOCK_50), .KEY(1'b0), .LCD_EN(LCD_EN), .LCD_RW(LCD_RW), .LCD_RS(LCD_RS), .LCD_DATA(LCD_DATA), .LCD_ON(LCD_ON), .LCD_BLON(LCD_BLON), .if_data(if_data), .if_write(if_write), .if_ready(if_ready) ); initial begin if_data <= 32'habba0123; state <= IDLE; if_write <= 1'b0; cntr <= 32'b0; end always@ (posedge CLOCK_50) begin case (state) IDLE: if (if_ready) begin if_data <= if_data + 1'b1; if_write <= 1'b1; state <= IF_WRITE_1; cntr <= 32'b0; end IF_WRITE_1: // this state to keep if_write up for 2 cycles state <= SET_IF_WRITE_0; SET_IF_WRITE_0: // set if_write 0 and start the counter begin if_write <= 1'b0; state <= WAIT; cntr <= 32'b0; end WAIT: if (cntr < 25000000) // wait for 0.5 seconds cntr <= cntr + 32'b1; else state <= IDLE; endcase end endmodule
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