fast_adder4b.v

各种滤波器的设计方法

module fast_adder4b(ina,inb,carry_in,sum_out,clk,rst_n);

parameter    ADDER_WIDTH = 4;
parameter    SUM_WIDTH = 5;

input  [ADDER_WIDTH-1:0]    ina;
input  [ADDER_WIDTH-1:0]    inb;
input                       carry_in;
input                       rst_n;
input                       clk;

output [SUM_WIDTH -1:0]     sum_out;

reg    [SUM_WIDTH -1:0]     sum_out;

wire   [ADDER_WIDTH-1:0]    sg; 
wire   [ADDER_WIDTH-1:0]    sp;
wire   [ADDER_WIDTH-1:0]    sc;

assign  sg[0]=ina[0]&inb[0];  
assign  sg[1]=ina[1]&inb[1];  
assign  sg[2]=ina[2]&inb[2];  
assign  sg[3]=ina[3]&inb[3];

assign  sp[0]=ina[0]^inb[0];  
assign  sp[1]=ina[1]^inb[1];  
assign  sp[2]=ina[2]^inb[2];  
assign  sp[3]=ina[3]^inb[3];  

assign  sc[0]= sg[0]|(sp[0] & carry_in);	//超前进位逻辑                                       
assign  sc[1]= sg[1]|(sp[1] & (sg[0] | (sp[0] & carry_in)));                                   
assign  sc[2]= sg[2]|(sp[2] & (sg[1] | (sp[1] & (sg[0] | (sp[0] & carry_in)))));            
assign  sc[3]= sg[3]|(sp[3] & (sg[2] | (sp[2] & (sg[1] | (sp[1] & (sg[0] | (sp[0] & carry_in)))))));

always @(posedge clk or negedge rst_n)
begin
  if(!rst_n)
    sum_out <= 5'b00000;
  else
    begin
      sum_out[0] <= sp[0] ^ carry_in;		//求和逻辑
      sum_out[1] <= sp[1] ^ sc[0];
      sum_out[2] <= sp[2] ^ sc[1];
      sum_out[3] <= sp[3] ^ sc[2];
      sum_out[4] <= sc[3];
    end
end

endmodule