mul4b_shiftadd_fsm.v

来自「各种滤波器的设计方法」· Verilog 代码 · 共 68 行

module mul4b_shiftadd_fsm(mul_a,mul_b,mul_out,clk,rst_n);

parameter MUL_WIDTH = 4;
parameter MUL_RESULT = 8;
parameter s0 = 0;
parameter s1 = 1;
parameter s2 = 2;

input     [MUL_WIDTH-1:0]      mul_a;
input     [MUL_WIDTH-1:0]      mul_b;
input                          clk;
input                          rst_n;

output    [MUL_RESULT-1:0]     mul_out;

reg       [MUL_RESULT-1:0]     mul_out;
reg       [MUL_RESULT-1:0]     p;
reg       [MUL_RESULT-1:0]     t;
reg       [MUL_WIDTH-1:0]      mul_areg;
reg       [2:0]                count;
reg       [1:0]                state;

always @(posedge clk or negedge rst_n)
begin
  if(!rst_n)
    begin
      mul_out <= 8'b0000_0000;
      p <= 8'b0000_0000;
      t <= 8'b0000_0000;
      mul_areg <= 4'b0000;
      count = 3'b000;
      state <= s0;
    end
  else
    begin
      case (state)
        s0 : 
           begin
             mul_areg <= mul_a;
             state <= s1;
             count = 2'b00;
             p <= 8'b0000_0000;
             t <= {1'b0,1'b0,1'b0,1'b0,mul_b};
           end
        s1 :
           begin
             if(count==4)
               state <= s2;
             else
               begin
                 if(mul_areg[0]==1'b1)
                   p <= p + t;
                 mul_areg <= mul_areg >> 1;
                 t <= t << 1;
                 count = count + 1;
                 state <= s1;
               end
          end
       s2 :
          begin
            mul_out <= p;
            state <= s0;
          end
     endcase
   end
end
endmodule