msp430x22x4_clks_modified.c

430成都技术培训会代码

//******************************************************************************
//  MSP430F22xx Demo - Basic Clock, Output Buffered SMCLK, ACLK and MCLK/10
//
//  Description: Buffer ACLK on P2.0, default SMCLK(DCO) on P2.1 and MCLK/10 on
//  P1.0.
//  ACLK = LFXT1 = VLO, MCLK = SMCLK = default DCO
//  //* External watch crystal installed on XIN XOUT is required for ACLK *//	
//
//               MSP430F22x4
//             -----------------
//         /|\|              XIN|-
//          | |                 | 
//          --|RST          XOUT|-
//            |                 |
//            |        P2.0/ACLK|-->ACLK = VLO       
//            |       P2.1/SMCLK|-->SMCLK = Default DCO
//            |             P1.0|-->MCLK/10 = DCO/10
//            |                 |    
//
//  M. Buccini / L. Westlund
//  Texas Instruments Inc.
//  October 2005
//  Built with IAR Embedded Workbench Version: 3.42F
//******************************************************************************

#include  <msp430x22x4.h>

void main(void)
{
  volatile unsigned int i;
  WDTCTL = WDTPW +WDTHOLD;                  // Stop Watchdog Timer
  BCSCTL3 |= LFXT1S_2;                      // LFXT1 = VLO  
 // DCOCTL   = CALDCO_16MHZ;
 // BCSCTL1  = CALBC1_16MHZ;
  P1DIR |= BIT0;                            // P1.0 outputs
 
  P2DIR |= 0x03;
  P2SEL |= 0x03;                            // P2.0,1 ACLK, SMCLK output

  while(1)
  {
    P1OUT |= BIT0;    	                    // P1.0 = 1
    for(i=50000;i>0;i--);                   // Delay
    P1OUT &= ~BIT0;                         // P1.0 = 0
     for(i=50000;i>0;i--);                   // Delay
  }
}