pcitohpi16.vhd

主机通过pci9054与c6713的hpi接口读取dsp的所有内外存

----------------------------------------------------------------------------------
-- Company: ioe
-- Engineer: dingke
-- 
-- Create Date:    16:00:14 04/15/2008 
-- Design Name:    pci to hpi of c6713
-- Module Name:    vhdl1 - Behavioral 
-- Project Name:   dsp-fpga-dpram-pci-host
-- Target Devices: 
-- Tool versions: 
-- Description:  for host to read or write the internal or outernal memeory 
--through the ecomomic host port interface
-- Revision: 
-- Revision 0.01 - File Created
-- Additional Comments: 
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
library UNISIM;
use UNISIM.VComponents.all;

entity vhdl1 is
	generic (
		-- System Port / Port B
		NumberOfSysDataBits : integer := 16;
		NumberOfSysAddrBits : integer := 3
		--you can change the number of the address lines here without modificaions in the whole code.
	);
	 port (
	     
	     dsprst: in std_logic;
		  flashrst: out std_logic;
          -- Internal or system side
		  lhold: in std_logic;   ---request for the local bus;
		  lholda: out std_logic;   ---grant the pci for the bus;
		  ads: in std_logic;
		  blast: in std_logic;
		  lbe1:in std_logic;   ---16bit pci use
		  --lbe0: in std_logic;  ---8bit pci use!!
		  lwr: in std_logic;----read or write signal
        ready: out std_logic; 
		  pciClk		: in std_logic;---50Mhz
        ---pciRst		: in std_logic;---connected to the lint?
        laddr  : in std_logic_vector (NumberOfSysAddrBits-1 downto 1);    ---0 for 32bit,1 for 16 bit ,2 for 8bit;  -- Address can be different width.
        ldata	: Inout std_logic_vector (NumberOfSysDataBits-1 downto 0); -- Data can be different width.
		  ---pci's pullup or pulldown for the fpga's chaos
		  bterm: out std_logic;
		  --lserr:out std_logic;
		  ---breqo:out std_logic;
		  breqi:out std_logic;
		  wait1:out std_logic;
		  --lreset:out std_logic;
		  --eot:out std_logic;
		  lint:out std_logic;
		  dreqo:out std_logic;
		  --dacko:out std_logic;
		  ccs:out std_logic;
		  bigend:out std_logic;
		  -----hpi side of c6713b
		  
		  hdata	: Inout std_logic_vector (NumberOfSysDataBits-1 downto 0);
		  hrw: out std_logic;
		  hcntl: out std_logic_vector (2 downto 1); ---address of the regesiters(HPIA/C/D)
		  --00 for hpic,01 for hpia,10 for hpid in autoincrement mode, 11 for hpid in fixed address mode;
		  hhwil: out std_logic; ---halfword identifier
		  hrdy: in std_logic; 
		  hcs: out std_logic;
		  hds1:out std_logic;----to produce the data stobe!
		  hds2:out std_logic;
		  has: out std_logic---not used,tied high.
		 -- hint: out std_logic; ----to interrupt the host.
		  );


end vhdl1;

architecture Behavioral of vhdl1 is

signal hstrobe : std_logic_vector (1 downto 0);

signal data1,data2 : std_logic_vector (NumberOfSysDataBits-1 downto 0);

signal ready1: std_logic;----to handle the problem that the out mode can't be read?

signal ready2: std_logic;

signal rst: std_logic;
begin

        bterm<='1';
		  --lserr<='1';
		  --breqo<='1';
		  breqi<='0';
		  wait1<='1';
		  --lreset<='1';
		  --eot<='1';
		  lint<='1';
		  dreqo<='1';
		  --dacko<='1';
		  ccs<='1';
		  bigend<='1';

flashrst<=dsprst; 

----hpi side
has<='1'; --tide high indicate no latch signal to hpi.
hds1<='1';--- use hds2 to produce the strobe!
hrw<= not lwr;
---ERROR!ldata is driving non-buffer!---hdata<=ldata;
hhwil<=lbe1;
hcntl(2)<=laddr(2);----control signal;
hcntl(1)<=laddr(1);

hstrobe(0)<=ads;
hstrobe(1)<=blast;----combine the signal;

process(dsprst)

begin

if (dsprst='0') then 

pcitohpi:process(pciClk)-----write.

begin

if (pciClk'event and pciClk='1') then 
 
    if lhold='1' then lholda<='1'; hcs<='0'; else lholda<='0';hcs<='1'; end if;
	 
	 if ads='0' then ready2<='1'; else ready2<='0'; end if;
	 
 case hstrobe is
	 
	 when "11" => hds2<='1';
	 
	 when "10" => hds2<='0';
	 
	 when "01" => 
	 
	 if ready1='0' then hds2<='1';
	 
	 else hds2<='0'; end if;
	 
	 when others=> hds2<='X';
	 
  end case;

end if;

end process;

ready<=hrdy or ready2;

ready1<=hrdy or ready2;

write: PROCESS(lwr,blast,ready1,ldata)

begin  

 if (lwr='1' and  blast='0' and ready1='0') then
 
   data1<=ldata;
 
 else data1<="ZZZZZZZZZZZZZZZZ";
 
 end if;
 
   hdata<=data1;
 
 end process;
 
--read: PROCESS(pciClk)

 --begin  
 
--if (pciClk'event and pciClk='1') then 

-- if (lwr='0' and  blast='0' and ready1='0') then
 
--    data2<=hdata;
 
-- else data2<="ZZZZZZZZZZZZZZZZ";
 
-- end if; 
 
-- end if;
  
--end process;
 
--ldata<=data2;
--hdata<=ldata when( lwr='1' and  blast='0' and ready1='0') else (others=>'Z');---pci write the hpi

ldata<=hdata when( lwr='0' and  blast='0' and ready1='0' ) else (others=>'Z'); ----pci read the hpi data;



end Behavioral;