sanjiaobo.vht

这是一个用abel语言编写的三角波发生器

-- VHDL Test Bench Created from source file sanjiaobo.vhd -- Sat Dec 22 16:45:22 2007
--
-- Notes: 
-- 1) This testbench template has been automatically generated using types
-- std_logic and std_logic_vector for the ports of the unit under test.
-- Lattice recommends that these types always be used for the top-level
-- I/O of a design in order to guarantee that the testbench will bind
-- correctly to the timing (post-route) simulation model.
-- 2) To use this template as your testbench, change the filename to any
-- name of your choice with the extension .vhd, and use the "source->import"
-- menu in the ispDesignExpert System Project Navigator to import the testbench.
-- Then edit the user defined section below, adding code to generate the 
-- stimulus for your design.
--
LIBRARY ieee;
LIBRARY generics;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
USE generics.components.ALL;

ENTITY testbench IS
END testbench;

ARCHITECTURE behavior OF testbench IS 

	COMPONENT sanjiaobo
	PORT(
		CP : IN std_logic;
		CONTROL : IN std_logic;          
		Q5 : OUT std_logic;
		Q4 : OUT std_logic;
		Q3 : OUT std_logic;
		Q2 : OUT std_logic;
		Q1 : OUT std_logic;
		Q0 : OUT std_logic
		);
	END COMPONENT;

	SIGNAL Q5 :  std_logic;
	SIGNAL Q4 :  std_logic;
	SIGNAL Q3 :  std_logic;
	SIGNAL Q2 :  std_logic;
	SIGNAL Q1 :  std_logic;
	SIGNAL Q0 :  std_logic;
	SIGNAL CP :  std_logic;
	SIGNAL CONTROL :  std_logic;

BEGIN

	uut: sanjiaobo PORT MAP(
		Q5 => Q5,
		Q4 => Q4,
		Q3 => Q3,
		Q2 => Q2,
		Q1 => Q1,
		Q0 => Q0,
		CP => CP,
		CONTROL => CONTROL
	);


-- *** Test Bench - User Defined Section ***
   tb : PROCESS
   BEGIN
      wait; -- will wait forever
   END PROCESS;
-- *** End Test Bench - User Defined Section ***

END;