sanjiaobo.edn

这是一个用abel语言编写的三角波发生器

(edif sanjiaobo
  (edifVersion 2 0 0)
  (edifLevel 0)
  (keywordMap (keywordLevel 0))
  (status (written
    (timeStamp 107 12 22 16 39 27)
    (program "blif2net" (version "ispDesignEXPERT 8.3"))))

  (external plsi
    (edifLevel 0)
    (technology (numberDefinition))

    (cell AND2
      (cellType GENERIC)
      (view NetList
        (viewType NETLIST)
        (interface
          (port A0 (direction INPUT))
          (port A1 (direction INPUT))
          (port Z0 (direction OUTPUT))
        )
      )
    )

    (cell AND3
      (cellType GENERIC)
      (view NetList
        (viewType NETLIST)
        (interface
          (port A0 (direction INPUT))
          (port A1 (direction INPUT))
          (port A2 (direction INPUT))
          (port Z0 (direction OUTPUT))
        )
      )
    )

    (cell AND4
      (cellType GENERIC)
      (view NetList
        (viewType NETLIST)
        (interface
          (port A0 (direction INPUT))
          (port A1 (direction INPUT))
          (port A2 (direction INPUT))
          (port A3 (direction INPUT))
          (port Z0 (direction OUTPUT))
        )
      )
    )

    (cell INV
      (cellType GENERIC)
      (view NetList
        (viewType NETLIST)
        (interface
          (port A0 (direction INPUT))
          (port ZN0 (direction OUTPUT))
        )
      )
    )

    (cell NAND2
      (cellType GENERIC)
      (view NetList
        (viewType NETLIST)
        (interface
          (port A0 (direction INPUT))
          (port A1 (direction INPUT))
          (port ZN0 (direction OUTPUT))
        )
      )
    )

    (cell IB11
      (cellType GENERIC)
      (view NetList
        (viewType NETLIST)
        (interface
          (port XI0 (direction INPUT))
          (port Z0 (direction OUTPUT))
        )
      )
    )

    (cell OB11
      (cellType GENERIC)
      (view NetList
        (viewType NETLIST)
        (interface
          (port A0 (direction INPUT))
          (port XO0 (direction OUTPUT))
        )
      )
    )

    (cell FD11
      (cellType GENERIC)
      (view NetList
        (viewType NETLIST)
        (interface
          (port CLK (direction INPUT))
          (port D0 (direction INPUT))
          (port Q0 (direction OUTPUT))
        )
      )
    )
  )

  (library sanjiaobo
    (edifLevel 0)
    (technology (numberDefinition))

    (cell sanjiaobo
      (cellType GENERIC)
      (view NetList
        (viewType NETLIST)
        (interface
          (port CONTROL (direction INPUT))
          (port Q5 (direction OUTPUT))
          (port Q4 (direction OUTPUT))
          (port Q3 (direction OUTPUT))
          (port Q2 (direction OUTPUT))
          (port Q1 (direction OUTPUT))
          (port Q0 (direction OUTPUT))
          (port CP (direction INPUT))
        )

        (contents
          (instance IN_CONTROL_U1 (viewRef NetList (cellRef IB11 (libraryRef plsi))))
          (instance OUT_Q5_U1 (viewRef NetList (cellRef OB11 (libraryRef plsi))))
          (instance OUT_Q4_U1 (viewRef NetList (cellRef OB11 (libraryRef plsi))))
          (instance OUT_Q3_U1 (viewRef NetList (cellRef OB11 (libraryRef plsi))))
          (instance OUT_Q2_U1 (viewRef NetList (cellRef OB11 (libraryRef plsi))))
          (instance OUT_Q1_U1 (viewRef NetList (cellRef OB11 (libraryRef plsi))))
          (instance OUT_Q0_U1 (viewRef NetList (cellRef OB11 (libraryRef plsi))))
          (instance IN_CP_U1 (viewRef NetList (cellRef IB11 (libraryRef plsi))))
          (instance FF_Q5_U1 (viewRef NetList (cellRef FD11 (libraryRef plsi))))
          (instance FF_Q4_U1 (viewRef NetList (cellRef FD11 (libraryRef plsi))))
          (instance FF_Q3_U1 (viewRef NetList (cellRef FD11 (libraryRef plsi))))
          (instance FF_Q2_U1 (viewRef NetList (cellRef FD11 (libraryRef plsi))))
          (instance FF_Q1_U1 (viewRef NetList (cellRef FD11 (libraryRef plsi))))
          (instance FF_Q0_U1 (viewRef NetList (cellRef FD11 (libraryRef plsi))))
          (instance GATE_Q5_D_REG_U1 (viewRef NetList (cellRef AND4 (libraryRef plsi))))
          (instance GATE_Q4_D_REG_I_4 (viewRef NetList (cellRef AND3 (libraryRef plsi))))
          (instance GATE_Q3_D_REG_I_4 (viewRef NetList (cellRef AND3 (libraryRef plsi))))
          (instance GATE_Q2_D_REG_I_4 (viewRef NetList (cellRef AND3 (libraryRef plsi))))
          (instance GATE_Q1_D_REG_I_4 (viewRef NetList (cellRef AND3 (libraryRef plsi))))
          (instance GATE_Q0_D_REG_I_4 (viewRef NetList (cellRef AND3 (libraryRef plsi))))
          (instance GATE_T__0_I_3 (viewRef NetList (cellRef NAND2 (libraryRef plsi))))
          (instance GATE_T__0_I_2 (viewRef NetList (cellRef INV (libraryRef plsi))))
          (instance GATE_T__0_I_1 (viewRef NetList (cellRef INV (libraryRef plsi))))
          (instance GATE_T__1_I_3 (viewRef NetList (cellRef NAND2 (libraryRef plsi))))
          (instance GATE_T__1_I_2 (viewRef NetList (cellRef INV (libraryRef plsi))))
          (instance GATE_T__1_I_1 (viewRef NetList (cellRef INV (libraryRef plsi))))
          (instance GATE_T__2_I_3 (viewRef NetList (cellRef NAND2 (libraryRef plsi))))
          (instance GATE_T__2_I_2 (viewRef NetList (cellRef INV (libraryRef plsi))))
          (instance GATE_T__2_I_1 (viewRef NetList (cellRef INV (libraryRef plsi))))
          (instance GATE_T__3_I_3 (viewRef NetList (cellRef NAND2 (libraryRef plsi))))
          (instance GATE_T__3_I_2 (viewRef NetList (cellRef INV (libraryRef plsi))))
          (instance GATE_T__3_I_1 (viewRef NetList (cellRef INV (libraryRef plsi))))
          (instance GATE_T__4_I_3 (viewRef NetList (cellRef NAND2 (libraryRef plsi))))
          (instance GATE_T__4_I_2 (viewRef NetList (cellRef INV (libraryRef plsi))))
          (instance GATE_T__4_I_1 (viewRef NetList (cellRef INV (libraryRef plsi))))
          (instance GATE_T__5_I_2 (viewRef NetList (cellRef INV (libraryRef plsi))))
          (instance GATE_T__5_I_1 (viewRef NetList (cellRef INV (libraryRef plsi))))
          (instance GATE_T__5_U1 (viewRef NetList (cellRef AND2 (libraryRef plsi))))
          (instance GATE_T__6_I_1 (viewRef NetList (cellRef INV (libraryRef plsi))))
          (instance GATE_T__6_U1 (viewRef NetList (cellRef AND2 (libraryRef plsi))))
          (instance GATE_T__7_I_4 (viewRef NetList (cellRef AND3 (libraryRef plsi))))
          (instance GATE_T__7_U3 (viewRef NetList (cellRef INV (libraryRef plsi))))
          (instance GATE_T__7_I_2 (viewRef NetList (cellRef INV (libraryRef plsi))))
          (instance GATE_T__8_I_4 (viewRef NetList (cellRef AND3 (libraryRef plsi))))
          (instance GATE_T__8_I_2 (viewRef NetList (cellRef INV (libraryRef plsi))))
          (instance GATE_T__9_I_4 (viewRef NetList (cellRef AND3 (libraryRef plsi))))
          (instance GATE_T__9_U3 (viewRef NetList (cellRef INV (libraryRef plsi))))
          (instance GATE_T__9_I_2 (viewRef NetList (cellRef INV (libraryRef plsi))))
          (instance GATE_T__10_I_4 (viewRef NetList (cellRef AND3 (libraryRef plsi))))
          (instance GATE_T__10_I_2 (viewRef NetList (cellRef INV (libraryRef plsi))))
          (instance GATE_T__11_I_4 (viewRef NetList (cellRef AND3 (libraryRef plsi))))
          (instance GATE_T__11_U3 (viewRef NetList (cellRef INV (libraryRef plsi))))
          (instance GATE_T__11_I_2 (viewRef NetList (cellRef INV (libraryRef plsi))))
          (instance GATE_T__12_I_4 (viewRef NetList (cellRef AND3 (libraryRef plsi))))
          (instance GATE_T__12_I_2 (viewRef NetList (cellRef INV (libraryRef plsi))))
          (instance GATE_T__13_I_4 (viewRef NetList (cellRef AND3 (libraryRef plsi))))
          (instance GATE_T__13_U3 (viewRef NetList (cellRef INV (libraryRef plsi))))
          (instance GATE_T__13_I_2 (viewRef NetList (cellRef INV (libraryRef plsi))))
          (instance GATE_T__14_I_4 (viewRef NetList (cellRef AND3 (libraryRef plsi))))
          (instance GATE_T__14_I_2 (viewRef NetList (cellRef INV (libraryRef plsi))))
          (instance GATE_T__15_I_2 (viewRef NetList (cellRef INV (libraryRef plsi))))
          (instance GATE_T__15_I_1 (viewRef NetList (cellRef INV (libraryRef plsi))))
          (instance GATE_T__15_U1 (viewRef NetList (cellRef AND2 (libraryRef plsi))))
          (instance GATE_T__16_I_2 (viewRef NetList (cellRef INV (libraryRef plsi))))
          (instance GATE_T__16_I_1 (viewRef NetList (cellRef INV (libraryRef plsi))))
          (instance GATE_T__16_U1 (viewRef NetList (cellRef AND2 (libraryRef plsi))))
          (instance GATE_T__17_I_2 (viewRef NetList (cellRef INV (libraryRef plsi))))
          (instance GATE_T__17_I_1 (viewRef NetList (cellRef INV (libraryRef plsi))))
          (instance GATE_T__17_U1 (viewRef NetList (cellRef AND2 (libraryRef plsi))))
          (instance GATE_T__18_I_2 (viewRef NetList (cellRef INV (libraryRef plsi))))
          (instance GATE_T__18_I_1 (viewRef NetList (cellRef INV (libraryRef plsi))))
          (instance GATE_T__18_U1 (viewRef NetList (cellRef AND2 (libraryRef plsi))))
          (instance GATE_T__19_I_2 (viewRef NetList (cellRef INV (libraryRef plsi))))
          (instance GATE_T__19_I_1 (viewRef NetList (cellRef INV (libraryRef plsi))))
          (instance GATE_T__19_U1 (viewRef NetList (cellRef AND2 (libraryRef plsi))))
          (instance GATE_T__20_I_2 (viewRef NetList (cellRef INV (libraryRef plsi))))
          (instance GATE_T__20_I_1 (viewRef NetList (cellRef INV (libraryRef plsi))))
          (instance GATE_T__20_U1 (viewRef NetList (cellRef AND2 (libraryRef plsi))))
          (instance GATE_T__21_I_2 (viewRef NetList (cellRef INV (libraryRef plsi))))
          (instance GATE_T__21_I_1 (viewRef NetList (cellRef INV (libraryRef plsi))))
          (instance GATE_T__21_U1 (viewRef NetList (cellRef AND2 (libraryRef plsi))))
          (instance GATE_T__22_I_2 (viewRef NetList (cellRef INV (libraryRef plsi))))
          (instance GATE_T__22_I_1 (viewRef NetList (cellRef INV (libraryRef plsi))))
          (instance GATE_T__22_U1 (viewRef NetList (cellRef AND2 (libraryRef plsi))))
          (instance GATE_T__23_I_2 (viewRef NetList (cellRef INV (libraryRef plsi))))
          (instance GATE_T__23_I_1 (viewRef NetList (cellRef INV (libraryRef plsi))))
          (instance GATE_T__23_U1 (viewRef NetList (cellRef AND2 (libraryRef plsi))))
          (instance GATE_T__24_I_2 (viewRef NetList (cellRef INV (libraryRef plsi))))
          (instance GATE_T__24_I_1 (viewRef NetList (cellRef INV (libraryRef plsi))))
          (instance GATE_T__24_U1 (viewRef NetList (cellRef AND2 (libraryRef plsi))))
          (instance GATE_T__25_I_2 (viewRef NetList (cellRef INV (libraryRef plsi))))
          (instance GATE_T__25_I_1 (viewRef NetList (cellRef INV (libraryRef plsi))))
          (instance GATE_T__25_U1 (viewRef NetList (cellRef AND2 (libraryRef plsi))))
          (instance GATE_T__26_I_2 (viewRef NetList (cellRef INV (libraryRef plsi))))
          (instance GATE_T__26_I_1 (viewRef NetList (cellRef INV (libraryRef plsi))))
          (instance GATE_T__26_U1 (viewRef NetList (cellRef AND2 (libraryRef plsi))))
          (instance GATE_T__27_I_1 (viewRef NetList (cellRef INV (libraryRef plsi))))
          (instance GATE_T__27_U1 (viewRef NetList (cellRef AND2 (libraryRef plsi))))

          (net CONTROL (joined
            (portRef CONTROL)
            (portRef XI0 (instanceRef IN_CONTROL_U1))
          ))

          (net CONTROL_PIN_BLIF (joined
            (portRef Z0 (instanceRef IN_CONTROL_U1))
            (portRef A0 (instanceRef GATE_Q5_D_REG_U1))
            (portRef A0 (instanceRef GATE_T__5_I_2))
            (portRef A1 (instanceRef GATE_T__6_U1))
            (portRef A0 (instanceRef GATE_T__7_I_2))
            (portRef A1 (instanceRef GATE_T__8_I_4))
            (portRef A0 (instanceRef GATE_T__9_I_2))
            (portRef A1 (instanceRef GATE_T__10_I_4))
            (portRef A0 (instanceRef GATE_T__11_I_2))
            (portRef A1 (instanceRef GATE_T__12_I_4))
            (portRef A0 (instanceRef GATE_T__13_I_2))
            (portRef A1 (instanceRef GATE_T__14_I_4))
          ))

          (net Q5 (joined
            (portRef Q5)
            (portRef XO0 (instanceRef OUT_Q5_U1))
          ))

          (net Q5_Q_BLIF (joined
            (portRef A0 (instanceRef OUT_Q5_U1))
            (portRef Q0 (instanceRef FF_Q5_U1))
            (portRef A0 (instanceRef GATE_T__5_I_1))
            (portRef A2 (instanceRef GATE_T__13_I_4))
            (portRef A0 (instanceRef GATE_T__14_I_2))
            (portRef A0 (instanceRef GATE_T__18_I_1))
            (portRef A0 (instanceRef GATE_T__20_I_1))
            (portRef A0 (instanceRef GATE_T__22_I_1))
            (portRef A0 (instanceRef GATE_T__27_I_1))
          ))

          (net Q4 (joined
            (portRef Q4)
            (portRef XO0 (instanceRef OUT_Q4_U1))
          ))

          (net Q4_Q_BLIF (joined
            (portRef A0 (instanceRef OUT_Q4_U1))
            (portRef Q0 (instanceRef FF_Q4_U1))
            (portRef A2 (instanceRef GATE_T__11_I_4))
            (portRef A0 (instanceRef GATE_T__12_I_2))
            (portRef A0 (instanceRef GATE_T__16_I_1))
            (portRef A0 (instanceRef GATE_T__18_I_2))
            (portRef A0 (instanceRef GATE_T__20_I_2))
            (portRef A0 (instanceRef GATE_T__24_I_1))
            (portRef A1 (instanceRef GATE_T__27_U1))
          ))

          (net Q3 (joined
            (portRef Q3)
            (portRef XO0 (instanceRef OUT_Q3_U1))
          ))

          (net Q3_Q_BLIF (joined
            (portRef A0 (instanceRef OUT_Q3_U1))
            (portRef Q0 (instanceRef FF_Q3_U1))
            (portRef A2 (instanceRef GATE_T__9_I_4))
            (portRef A0 (instanceRef GATE_T__10_I_2))
            (portRef A0 (instanceRef GATE_T__13_U3))
            (portRef A2 (instanceRef GATE_T__14_I_4))
            (portRef A0 (instanceRef GATE_T__16_I_2))
            (portRef A0 (instanceRef GATE_T__17_I_1))
            (portRef A0 (instanceRef GATE_T__22_I_2))
            (portRef A0 (instanceRef GATE_T__26_I_1))
          ))

          (net Q2 (joined
            (portRef Q2)
            (portRef XO0 (instanceRef OUT_Q2_U1))
          ))

          (net Q2_Q_BLIF (joined
            (portRef A0 (instanceRef OUT_Q2_U1))
            (portRef Q0 (instanceRef FF_Q2_U1))
            (portRef A2 (instanceRef GATE_T__7_I_4))
            (portRef A0 (instanceRef GATE_T__8_I_2))
            (portRef A0 (instanceRef GATE_T__11_U3))
            (portRef A2 (instanceRef GATE_T__12_I_4))
            (portRef A0 (instanceRef GATE_T__15_I_1))
            (portRef A0 (instanceRef GATE_T__19_I_1))
            (portRef A0 (instanceRef GATE_T__24_I_2))
            (portRef A0 (instanceRef GATE_T__26_I_2))
          ))

          (net Q1 (joined
            (portRef Q1)
            (portRef XO0 (instanceRef OUT_Q1_U1))
          ))

          (net Q1_Q_BLIF (joined
            (portRef A0 (instanceRef OUT_Q1_U1))
            (portRef Q0 (instanceRef FF_Q1_U1))
            (portRef A0 (instanceRef GATE_T__6_I_1))
            (portRef A0 (instanceRef GATE_T__9_U3))
            (portRef A2 (instanceRef GATE_T__10_I_4))
            (portRef A0 (instanceRef GATE_T__17_I_2))
            (portRef A0 (instanceRef GATE_T__21_I_1))
            (portRef A0 (instanceRef GATE_T__23_I_1))
            (portRef A0 (instanceRef GATE_T__25_I_1))
          ))

          (net Q0 (joined
            (portRef Q0)
            (portRef XO0 (instanceRef OUT_Q0_U1))
          ))

          (net Q0_Q_BLIF (joined
            (portRef A0 (instanceRef OUT_Q0_U1))
            (portRef Q0 (instanceRef FF_Q0_U1))
            (portRef A0 (instanceRef GATE_T__7_U3))
            (portRef A2 (instanceRef GATE_T__8_I_4))
            (portRef A0 (instanceRef GATE_T__15_I_2))
            (portRef A0 (instanceRef GATE_T__19_I_2))
            (portRef A0 (instanceRef GATE_T__21_I_2))
            (portRef A0 (instanceRef GATE_T__23_I_2))
            (portRef A0 (instanceRef GATE_T__25_I_2))
          ))

          (net CP (joined
            (portRef CP)
            (portRef XI0 (instanceRef IN_CP_U1))
          ))

          (net CP_PIN_BLIF (joined
            (portRef Z0 (instanceRef IN_CP_U1))
            (portRef CLK (instanceRef FF_Q5_U1))
            (portRef CLK (instanceRef FF_Q4_U1))
            (portRef CLK (instanceRef FF_Q3_U1))
            (portRef CLK (instanceRef FF_Q2_U1))
            (portRef CLK (instanceRef FF_Q1_U1))
            (portRef CLK (instanceRef FF_Q0_U1))
          ))

          (net Q5_D_REG (joined
            (portRef D0 (instanceRef FF_Q5_U1))
            (portRef Z0 (instanceRef GATE_Q5_D_REG_U1))
          ))

          (net Q4_D_REG (joined
            (portRef D0 (instanceRef FF_Q4_U1))
            (portRef Z0 (instanceRef GATE_Q4_D_REG_I_4))
          ))

          (net Q3_D_REG (joined
            (portRef D0 (instanceRef FF_Q3_U1))
            (portRef Z0 (instanceRef GATE_Q3_D_REG_I_4))
          ))

          (net Q2_D_REG (joined
            (portRef D0 (instanceRef FF_Q2_U1))
            (portRef Z0 (instanceRef GATE_Q2_D_REG_I_4))
          ))

          (net Q1_D_REG (joined
            (portRef D0 (instanceRef FF_Q1_U1))
            (portRef Z0 (instanceRef GATE_Q1_D_REG_I_4))
          ))

          (net Q0_D_REG (joined
            (portRef D0 (instanceRef FF_Q0_U1))
            (portRef Z0 (instanceRef GATE_Q0_D_REG_I_4))
          ))