bt865.c

linux TV 源码

/* 
   BT865A - Brook Tree BT865A video encoder driver version 0.0.4

   Henrik Johannson <[e-mail]>
   As modified by Chris C. Hoover <[e-mail]>
   
   This program is free software; you can redistribute it and/or modify
   it under the terms of the GNU General Public License as published by
   the Free Software Foundation; either version 2 of the License, or
   (at your option) any later version.

   This program is distributed in the hope that it will be useful,
   but WITHOUT ANY WARRANTY; without even the implied warranty of
   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
   GNU General Public License for more details.

   You should have received a copy of the GNU General Public License
   along with this program; if not, write to the Free Software
   Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
*/

#include <linux/module.h>
#include <linux/delay.h>
#include <linux/errno.h>
#include <linux/fs.h>
#include <linux/kernel.h>
#include <linux/major.h>
#include <linux/slab.h>
#include <linux/mm.h>
#include <linux/pci.h>
#include <linux/signal.h>
#include <asm/io.h>
#include <asm/pgtable.h>
#include <asm/page.h>
#include <linux/sched.h>
#include <asm/segment.h>
#include <linux/types.h>
#include <linux/wrapper.h>

#include <linux/videodev.h>
#include <linux/version.h>
#include <asm/uaccess.h>

#include <linux/i2c-algo-bit.h>
#include <linux/video_encoder.h>

#include "bt865.h"

#include "encoder.h"

#ifdef MODULE
static int color_bars = 0;
MODULE_PARM(color_bars, "i");

#if LINUX_VERSION_CODE > KERNEL_VERSION(2,4,9)
MODULE_LICENSE("GPL");
#endif

#endif

#define i2c_is_isa_client(clientptr) \
		((clientptr)->adapter->algo->id == I2C_ALGO_ISA)
#define i2c_is_isa_adapter(adapptr) \
		((adapptr)->algo->id == I2C_ALGO_ISA)


static int bt865_attach_adapter(struct i2c_adapter *adapter);
int bt865_detach_client(struct i2c_client *client);
int bt865_command(struct i2c_client *client, unsigned int cmd, void *arg);
void bt865_inc_use (struct i2c_client *client);
void bt865_dec_use (struct i2c_client *client);
static int bt865_setup(struct i2c_client *client);

struct bt865_data_s {
	int chiptype;
	int mode;
	int bars;
	int rgbmode;
	int enableoutput;

	unsigned char config[48];
	int configlen;
};

/* This is the driver that will be inserted */
static struct i2c_driver bt865_driver = {
  /* name */		"BT865 video encoder driver",
  /* id */		I2C_DRIVERID_BT865,
  /* flags */		I2C_DF_NOTIFY,
  /* attach_adapter */  &bt865_attach_adapter,
  /* detach_client */   &bt865_detach_client,
  /* command */		&bt865_command,
  /* inc_use */		&bt865_inc_use,
  /* dec_use */		&bt865_dec_use
};

int bt865_id = 0;

// Register settings come from Rockwell Semiconductor 
// Advance Information sheet l865a.pdf

// Bits from the Left for Register A0
// 1. one bit EWSF2 (Enable Wide Screen for Field 2)
//    enable/disable Wide Screen Signaling/Copy Generation Management 
//    System encoding for field 2 (16:9)
//    if 0 then Disable WSS/CGMS for Field 2
//    if 1 then Enable WSS/CGMS for Field 2
// 2. one bit EWSF1 (Enable Wide Screen for Field 1)
//    enable/disable Wide Screen Signaling/Copy Generation Management 
//    System encoding for field 1 (16:9)
//    if 0 then Disable WSS/CGMS for Field 1
//    if 1 then Enable WSS/CGMS for Field 1
// 3. two reserved bits, zero for normal operation
//    this should have been done by the reset above
// 4. four bits of WSDAT[1:4] (Wide Screen Data)

// Bits from the Left for Register A2
// 1. eight bits of WSDAT[5:12] (Wide Screen Data)

// Bits from the Left for Register A4
// 1. eight bits of WSDAT[13:20] (Wide Screen Data)
//    there is a typo in the document here. it Should Say A4

// Bits from the Left for Register A6
// 1. one bit SRESET (System Reset)
//    if 0 then Do Nothing
//    if 1 then Reset All Registers (including this one) To Zero
// 2. seven reserved bits, zero for normal operation
//    this should be done by the reset anyway

// Bits from the Left for Register A8
// 1. eight reserved bits, zero for normal operation
//    this should have been done by the reset above

// Bits from the Left for Register AA
// 1. eight reserved bits, zero for normal operation
//    this should have been done by the reset above

// Bits from the Left for Register AC
// 1. eight bits TXHS[7:0] (Rising Edge Position of TeleText Request Pin)
//    first eight bits of eleven

// Bits from the Left for Register AE
// 1. eight bits TXHE[7:0] (Falling Edge Position of TeleText Request Pin)
//    first eight bits of eleven

// Bits from the Left for Register B0
// 1. two bits LUMADLY[1:0] (Luminance Delay Mode, B Output)
//    D7   D6             Function
//    ----------------------------
//    0    0              No Delay
//    0    1              1 Pixel Clock Delay
//    1    0              2 Pixel Clock Delay
//    1    1              3 Pixel Clock Delay
//    used to program the Luminance Delay on the CVBS/B Output
// 2. three bits TXHE[10:8] (Last Three Bits Teletext Falling Edge) 
//    (Falling Edge Position of TeleText Request Pin)
// 3. three bits TXHS[10:8] (Last Three Bits Teletext Rising Edge) 
//    (Rising Edge Position of TeleText Request Pin)
// (It's a programmable pulse generator)

// Bits from the Left for Register B2
// 1. two reserved bits, zero for normal operation
//    this should have been done by the reset above
// 2. one bit TXRM (Teletext Request Mode)
//    if 0 then TTXREQ Pin outputs Request
//    if 1 then TTXREQ Pin outputs TTX Clock
// 3. one bit TXE (Teletext Enable)
//    if 0 then Disable Teletext
//    if 1 then Enable Teletext
// 4. one bit TXEF2[8] (Last Line of Teletext Field 2 (last bit)) 
// 5. one bit TXBF2[8] (First Line of Teletext Field 2 (last bit)) 
// 6. one bit TXEF1[8] (Last Line of Teletext Field 1 (last bit)) 
// 7. one bit TXBF1[8] (First Line of Teletext Field 1 (last bit)) 

// Bits from the Left for Register B4
// 1. eight bits TXBF1[7:0] (First Line of Teletext Field 1 
//    (first eight bits))

// Bits from the Left for Register B6
// 1. eight bits TXEF1[7:0] (Last Line of Teletext Field 1 
//    (first eight bits))

// Bits from the Left for Register B8
// 1. eight bits TXBF2[7:0] (First Line of Teletext Field 2 
//    (first eight bits))

// Bits from the Left for Register BA
// 1. eight bits TXEF2[7:0] (Last Line of Teletext Field 2
//    (first eight bits))

// Bits from the Left for Register BC
// 1. one bit ECCF2 (Enable Closed Caption Encoding on Field 2) 
//    if 0 then Disable Closed Caption Encoding on Field 2
//    if 1 then Enable Closed Caption Encoding on Field 2
// 2. one bit ECCF1 (Enable Closed Caption Encoding on Field 1) 
//    if 0 then Disable Closed Caption Encoding on Field 1
//    if 1 then Enable Closed Caption Encoding on Field 1
// 3. one bit ECCGATE (Closed Caption Mode)
//    if 0 then Normal Closed Caption Encoding 
//    if 1 then Prevent Encoding of Redundant or Incomplete Data
//         Future Encoding is Disabled Until a Complete Pair of 
//         New Data Bytes is Received
// 4. one reserved bit, zero for normal operation
//    this should have been done by the reset above
//    this is the bit that the original code mysteriously sets to one
// 5. one bit DACOFF (Turn Off DAC)
//    used to Limit Curent Consumption to Digital Circuits Only
//    if 0 then Normal Operation
//    if 1 then Disable DAC Output Current and Internal Voltage Reference
//    This Bit is Forced High After Powerup Until Either 8 Fields Have
//    Been Output or Register 0xCE Has Been Written
// 6. one bit YC16 (YC Mode)
//    if 0 then 8 Bit Mode: P[7:0] is Multiplexed YCrCb 8 Bit Video Data
//    if 1 then 16 Bit Mode: P[7:0] is Multiplexed CrCb 8 Bit Video Data
//                       and Y[7:0] is Y 8 Bit Data
// 7. one bit CBSWAP (Chroma Red/Blue Swap)
//    if 0 then Normal Pixel Sequence
//    if 1 then Cr and Cb Pixels are Swapped at the Input to the Pixel Port
// 8. one bit PORCH
//    if 0 then Front and Back Porch Timing Meets ITU-RBT.470-3
//         this must be the standard Porch Timing
//    if 1 then CCIR601 Porch Timing. This allows 720 Pixels Width
//         by Narrowing Front and Back Porch in Favor of Active Video

// Bits from the Left for Register BE
// 1. eight bits CCF2B1[7:0] (First Byte of Closed Captioning 
//    Information for Field 2)

// Bits from the Left for Register C0
// 1. eight bits CCF2B2[7:0] (Second Byte of Closed Captioning 
//    Information for Field 2)

// Bits from the Left for Register C2
// 1. eight bits CCF1B1[7:0] (First Byte of Closed Captioning 
//    Information for Field 1)

// Bits from the Left for Register C4
// 1. eight bits CCF1B2[7:0] (Second Byte of Closed Captioning 
//    Information for Field 1)

// Bits from the Left for Register C6
// 1. eight bits HSYNCF[7:0] (First Eight Bits Falling Edge Sync Data) 
//    SYNC Pulse Position Relative to Internal Horizontal Pixel Clock
//    for Falling Edge of HSYNC
// Needs ADJHSYNC = 1
// Master Mode Only

// Bits from the Left for Register C8
// 1. eight bits HSYNCR[7:0] (First Eight Bits Rising Edge Sync Data) 
//    SYNC Pulse Position Relative to Internal Horizontal Pixel Clock
//    for Rising Edge of HSYNC
// Needs ADJHSYNC = 1
// Master Mode Only

// Bits from the Left for Register CA
// 1. one bit SYNCDLY (Sync Delay Mode)
//    if 0 then Normal SYNC Timing
//    if 1 then Delayed SYNC Timing
//    set this to one to see a pretty green screen :)
// 2. one bit FIELD1 (the so-called Color Flag)
//    if 0 then If FIELD Pin = 1 this Indicates Field 2
//    if 1 then If FIELD Pin = 1 this Indicates Field 1
// 3. one bit SYNCDIS (VBI SYNC Mode)
//    if 0 then Normal HSYNC Operation
//    if 1 then Disable HSYNC Durring VBI (No H Serrations In VBI)
//    Master Mode Only
// 4. one bit ADJHSYNC (HSYNC Pulse Timing Mode)
//    if 0 then Normal 4.7usec HSYNC Pulse
//    if 1 then Use HSYNCR[10:0] and HSYNCF[10:0] to Program HSYNC Pulse
//         Rising and Falling Times
//    See HSYNCR[7:0] and HSYNCF[7:0] Above
//    (It's a programmable pulse generator and this is it's Enable Bit)
// 5. two bits HSYNCF[9:8] (Last Two Bits Falling Edge Sync Data) 
// 6. two bits HSYNCR[9:8] (Last Two Bits Rising Edge Sync Data) 

// Bits from the Left for Register CC
// 1. one bit SETMODE (Automatic Mode Detection)
//    if 0 then Use Automatic Mode Detection
//    if 1 then Override Automatic Mode Detection
//         Use VIDFORM[3:0], NONINTL and SQUARE Registers Bits to Set Mode
//    Slave Mode Only
// 2. one bit SETUPDIS (Disable 7.5 IRE Setup on Output)
//    if 0 then Setup On: 7.5 IRE Setup Enabled for Active Video Lines
//    if 1 then Setup Off: Disable 7.5 IRE Setup on Output Video
// 3. four bits VIDFORM[3:0]
//    These Bits Control the World Television Standard
//    D5  D4  D3  D2  Format         Market
//    -------------------------------------
//    0   0   0   0   NTSC Normal    USA/Japan
//    0   0   1   0   NTSC-60/HDTV   USA-HDTV (SCRESET Must Be 1)
//    1   1   0   0   PAL-M Normal   Brazil
//    1   1   1   0   PAL-M-60/HDTV  Brazil-HDTV
//    1   0   0   1   PAL-BDGHIN     Western Europe
//    1   1   0   1   PAL-NC         Argentina
// 4. one bit NONINTL (Non Interlace Mode)
//    if 0 then Interlaced Operation
//    if 1 then Non Interlaced Operation (Progressive Scan)
// 5. one bit SQUARE (Square Pixel Operation Mode)
//    if 0 then CCIR601 Operation
//    if 1 then Square Pixel Operation

// Bits from the Left for Register CE
// 1. one bit ESTATUS (I2C Readback Information Mode)
//    if 0 then I2C Readback Information Contains Version Number
//    if 1 then I2C Readback Information Contains Closed Caption Status
//         and Field Number
// 2. one bit RGBO (RGB Output Mode)
//    if 0 then Normal Operation
//    if 1 then Enable RGB Outputs
// 3. one bit DCHROMA (Disable Chroma)
//    if 0 then Normal Operation
//    if 1 then Disable Chroma (B/W Operation)
// 4. one bit ECBAR (Enable Color Bars)
//    if 0 then Normal Operation
//    if 1 then Enable Internally Generated Color Bars on Output
// 5. one bit SCRESET (Sub Carrier Reset Mode)
//    if 0 then Normal Operation 
//         (SC Phase is Reset at Beginning of Each Field)
//    if 1 then Disable Sub Carrier Reset Event at the
//         Beginning of Each Field Sequence
// 6. one bit EVBI (Enable HSYNC Durring VBI)
//    if 0 then Video is Blanked Durring Vertical Blanking Interval
//    if 1 then Enable Active Video Durring Vertical Blanking Interval
//         Setup is Added if SETUPDIS = 0
//         Scaling of YCrCb Pixels is based on 100% Blank to White
//         i.e. Normal PAL Input Scaling
// 7. one bit EACTIVE (Enable Active Video)
//    if 0 then Output Black With Burst if ECBAR = 0
//         or Color Bars if ECBAR = 1
//    if 1 then Normal Operation (Output Active Video)
// 8. one bit ECLIP (Enable DAC Clipping)
//    if 0 then Normal Operation
//    if 1 then DAC Values Less Than 31 Are Set To 31 (This Limit
//         Corresponds Roughly to 1/4 of Sync Height)

// Bits from the Left for Register D0
// 1. seven reserved bits, zero for normal operation
//    this should have been done by the reset above