skystar2.c

linux TV 源码

/*
 * skystar2.c - driver for the Technisat SkyStar2 PCI DVB card
 *              based on the FlexCopII by B2C2,Inc.
 *
 * Copyright (C) 2003  V.C. , [e-mail]
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU Lesser General Public License
 * as published by the Free Software Foundation; either version 2.1
 * of the License, or (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU Lesser General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA  02111-1307, USA.
 */
#include <linux/module.h>
#include <linux/delay.h>
#include <linux/pci.h>

#include "dmxdev.h"
#include "dvb_demux.h"
#include "dvb_i2c.h"
#include "dvb_frontend.h"
#include "dvb_net.h"


static int debug = 0;
#define dprintk	if(debug == 1) printk

#define SizeOfBufDMA1	0x3AC00
#define SizeOfBufDMA2	0x758

struct DmaQ {

    u32 bus_addr;
    u32 head;
    u32 tail;
    u32 buffer_size;
    u8 * buffer;
};

struct packet_header_t {

    u32 sync_byte;
    u32 transport_error_indicator;
    u32 payload_unit_start_indicator;
    u32 transport_priority;
    u32 pid;
    u32 transport_scrambling_control;
    u32 adaptation_field_control;
    u32 continuity_counter;
};

struct adapter {

    struct pci_dev *pdev;

    u8  card_revision;
    u32 B2C2_revision;
    u32 PidFilterMax;
    u32 MacFilterMax;
    u32 irq;
    u32 io_mem;
    u32 io_port;
    u8 mac_addr[8];
    u32 dwSramType;

    struct dvb_adapter * dvb_adapter;
    struct dvb_demux demux;    
    dmxdev_t dmxdev;	
    dmx_frontend_t hw_frontend;
    dmx_frontend_t mem_frontend;
    struct dvb_i2c_bus *i2c_bus;	
    struct dvb_net dvbnet;

    struct semaphore i2c_sem;

    struct DmaQ DmaQ1;
    struct DmaQ DmaQ2;

    u32 dma_ctrl;
    u32 dma_status;

    u32 capturing;

    spinlock_t  lock;

    u16 pids[0x27];
    u32 mac_filter;
};


//-------------------------------------------------------------------
void linuxdelayms(u32 usecs)
{
    while ( usecs > 0)
    {
	udelay(1000);

	usecs--;
    }
}

/////////////////////////////////////////////////////////////////////
//		register functions
/////////////////////////////////////////////////////////////////////

//-------------------------------------------------------------------
void WriteRegDW(struct adapter * adapter, u32 reg, u32 value)
{
    u32 flags;	

    save_flags(flags);
    cli();

    writel(value, adapter->io_mem + reg);

    restore_flags(flags);
}

//-------------------------------------------------------------------
u32 ReadRegDW(struct adapter * adapter, u32 reg)
{
    return readl(adapter->io_mem + reg);
}

//-------------------------------------------------------------------
u32 WriteRegOp(struct adapter * adapter, u32 reg, u32 operation, u32 andvalue, u32 orvalue)
{
    u32 tmp;	

    tmp = ReadRegDW(adapter, reg);

    if ( operation == 1 ) tmp = tmp | orvalue;
    if ( operation == 2 ) tmp = tmp & andvalue;
    if ( operation == 3 ) tmp = (tmp & andvalue) | orvalue;

    WriteRegDW(adapter, reg, tmp);

    return tmp;
}

/////////////////////////////////////////////////////////////////////
//			I2C
////////////////////////////////////////////////////////////////////

//-------------------------------------------------------------------
u32 i2cMainWriteForFlex2(struct adapter * adapter, u32 command, u8 * buf, u32 retries)
{
    u32 i;
    u32 value;

    WriteRegDW(adapter, 0x100, 0);
    WriteRegDW(adapter, 0x100, command);

    for ( i = 0; i < retries; i++ )
    {
	value = ReadRegDW(adapter, 0x100);

	if ( ( value & 0x40000000) == 0 )
	{
	    if ( ( value & 0x81000000 ) == 0x80000000 )
	    {
		if ( buf != 0 ) *buf = ( value >> 0x10 ) & 0xff;

		return 1;
	    }

	} else {
	    
	    WriteRegDW(adapter, 0x100, 0);
	    WriteRegDW(adapter, 0x100, command);
	}
    }

    return 0;
}

/////////////////////////////////////////////////////////////////////
//	device = 0x10000000 for tuner
//		 0x20000000 for eeprom
/////////////////////////////////////////////////////////////////////
//-------------------------------------------------------------------
u32 i2cMainSetup(u32 device, u32 chip_addr, u8 op, u8 addr, u32 value, u32 len)
{
    u32 command;

    command = device | ( (len-1) << 26 ) | ( value << 16 ) | ( addr << 8 ) | chip_addr;

    if ( op != 0 ) command = command | 0x03000000; else command = command | 0x01000000;
    
    return command;
}

//-------------------------------------------------------------------
u32 FlexI2cRead4(struct adapter * adapter, u32 device, u32 chip_addr, u16 addr, u8 * buf, u8 len)
{
    u32 command;
    u32 value;

    int result, i;

    command = i2cMainSetup(device, chip_addr, 1, addr, 0, len);

    result  = i2cMainWriteForFlex2(adapter, command, buf, 100000);

    if ( (result & 0xff) != 0 )
    {
	if ( len > 1 )
	{
	    value = ReadRegDW(adapter, 0x104);

	    for ( i = 1; i < len; i++ )
	    {
		buf[i] = value & 0xff;
		value = value >> 8;
	    }
	}
    }

    return result;
}

//-------------------------------------------------------------------
u32 FlexI2cWrite4(struct adapter * adapter, u32 device, u32 chip_addr, u32 addr, u8 * buf, u8 len)
{
    u32 command;
    u32 value;
    int i;

    if ( len > 1)
    {
	value = 0;
		
	for ( i = len; i > 1; i--)
	{
	    value = value << 8;
	    value = value | buf[i-1];
	}

	WriteRegDW(adapter, 0x104, value);
    }

    command = i2cMainSetup(device, chip_addr, 0, addr, buf[0], len);

    return i2cMainWriteForFlex2(adapter, command, 0, 100000);
}

//-------------------------------------------------------------------
u32 fixChipAddr(u32 device, u32 bus, u32 addr)
{
    if ( device == 0x20000000 ) return bus | ( ( addr >> 8 ) & 3 );

    return bus;
}

//-------------------------------------------------------------------
u32 FLEXI2C_read(struct adapter * adapter, u32 device, u32 bus, u32 addr, u8 * buf, u32 len)
{
    u32 ChipAddr;
    u32 bytes_to_transfer;
    u8 * start;

    dprintk("%s:\n", __FUNCTION__);

    start = buf;

    while ( len != 0 ) 
    {
	bytes_to_transfer = len;

	if ( bytes_to_transfer > 4 ) bytes_to_transfer = 4;
	
	ChipAddr = fixChipAddr(device, bus, addr);	

	if ( FlexI2cRead4(adapter, device, ChipAddr, addr, buf, bytes_to_transfer) == 0 ) return buf - start;

	buf = buf + bytes_to_transfer;
	addr = addr + bytes_to_transfer;
	len = len - bytes_to_transfer;
    };

    return buf - start;
}

//-------------------------------------------------------------------
u32 FLEXI2C_write(struct adapter * adapter, u32 device, u32 bus, u32 addr, u8 * buf, u32 len)
{
    u32 ChipAddr;
    u32 bytes_to_transfer;
    u8 * start;
    
    dprintk("%s:\n", __FUNCTION__);

    start = buf;

    while ( len != 0 ) 
    {
	bytes_to_transfer = len;

	if ( bytes_to_transfer > 4 ) bytes_to_transfer = 4;
	
	ChipAddr = fixChipAddr(device, bus, addr);	

	if ( FlexI2cWrite4(adapter, device, ChipAddr, addr, buf, bytes_to_transfer) == 0 ) return buf - start;

	buf = buf + bytes_to_transfer;
	addr = addr + bytes_to_transfer;
	len = len - bytes_to_transfer;
    }

    return buf - start;
}

static int master_xfer (struct dvb_i2c_bus * i2c, const struct i2c_msg * msgs, int num)
{
    struct adapter * tmp = i2c->data;
    int i, ret=0;

    if (down_interruptible (&tmp->i2c_sem)) return -ERESTARTSYS;
    
    if(0)
    {
	dprintk("%s:\n",__FUNCTION__);

	for(i=0; i<num; i++)
	{
	    printk("message %d: flags=%x, addr=0x%04x, buf=%x, len=%d \n", i, msgs[i].flags, msgs[i].addr, (u32)msgs[i].buf, msgs[i].len);
	}
    }			    

    // allow only the vp310 frontend to access the bus
    if ( ( msgs[0].addr != 0x0E) && ( msgs[0].addr != 0x61 ) )
    {
        up (&tmp->i2c_sem);	

	return -EREMOTEIO;
    }

    if ( ( num == 1 ) && ( msgs[0].buf != NULL ) )
    {
	if ( msgs[0].flags == I2C_M_RD )
	{
	    ret = -EINVAL;
		    
	} else {

	    // single writes do have the reg addr in buf[0] and data in buf[1] to buf[n]
	    ret = FLEXI2C_write(tmp, 0x10000000, msgs[0].addr, msgs[0].buf[0], &msgs[0].buf[1], msgs[0].len - 1);

	    if ( ret != msgs[0].len - 1)
		ret = -EREMOTEIO;
	    else
		ret = num;
	}

    } else if ( ( num == 2 ) && ( msgs[1].buf != NULL ) ) {
	    
	// i2c reads consist of a reg addr _write_ followed by a data read, so msg[1].flags has to be examined
	if ( msgs[1].flags == I2C_M_RD )
	{
	    ret = FLEXI2C_read(tmp, 0x10000000, msgs[0].addr, msgs[0].buf[0], msgs[1].buf, msgs[1].len);

	} else {

	    ret = FLEXI2C_write(tmp, 0x10000000, msgs[0].addr, msgs[0].buf[0], msgs[1].buf, msgs[1].len);
	}

	if (ret != msgs[1].len)
	    ret = -EREMOTEIO;
	else
	    ret = num;
    }

    up (&tmp->i2c_sem);

    // master xfer functions always return the number of successfully
    // transmitted messages, not the number of transmitted bytes.
    // return -EREMOTEIO in case of failure.
    return ret;
}

/////////////////////////////////////////////////////////////////////
// SRAM (Skystar2 rev2.3 has one "ISSI IS61LV256" chip on board,
// but it seems that FlexCopII can work with more than one chip)
/////////////////////////////////////////////////////////////////////
//-------------------------------------------------------------------
u32 SRAMSetNetDest(struct adapter *adapter, u8 dest)
{
    u32 tmp;

    udelay(1000);

    tmp = ( ReadRegDW(adapter, 0x714) & 0xFFFFFFFC ) | ( dest & 3 );

    udelay(1000);

    WriteRegDW(adapter, 0x714, tmp);
    WriteRegDW(adapter, 0x714, tmp);

    udelay(1000);

    return tmp;
}

//-------------------------------------------------------------------
u32 SRAMSetCaiDest(struct adapter *adapter, u8 dest)
{
    u32 tmp;

    udelay(1000);

    tmp = ( ReadRegDW(adapter, 0x714) & 0xFFFFFFF3 ) | ( ( dest & 3 ) << 2);

    udelay(1000);
    udelay(1000);

    WriteRegDW(adapter, 0x714, tmp);
    WriteRegDW(adapter, 0x714, tmp);

    udelay(1000);

    return tmp;
}

//-------------------------------------------------------------------
u32 SRAMSetCaoDest(struct adapter *adapter, u8 dest)
{
    u32 tmp;
    
    udelay(1000);

    tmp = ( ReadRegDW(adapter, 0x714) & 0xFFFFFFCF ) | ( ( dest & 3 ) << 4 );

    udelay(1000);
    udelay(1000);

    WriteRegDW(adapter, 0x714, tmp);
    WriteRegDW(adapter, 0x714, tmp);

    udelay(1000);

    return tmp;
}

//-------------------------------------------------------------------
u32 SRAMSetMediaDest(struct adapter *adapter, u8 dest)
{
    u32 tmp;
    
    udelay(1000);

    tmp = ( ReadRegDW(adapter, 0x714) & 0xFFFFFF3F ) | ( ( dest & 3 ) << 6 );

    udelay(1000);
    udelay(1000);

    WriteRegDW(adapter, 0x714, tmp);
    WriteRegDW(adapter, 0x714, tmp);

    udelay(1000);

    return tmp;
}

/////////////////////////////////////////////////////////////////////
// SRAM memory is accessed through a buffer register in the FlexCop
// chip (0x700). This register has the following structure:
//  bits 0-14  : address
//  bit  15    : read/write flag
//  bits 16-23 : 8-bit word to write
//  bits 24-27 : = 4
//  bits 28-29 : memory bank selector
//  bit  31    : busy flag
////////////////////////////////////////////////////////////////////
//-------------------------------------------------------------------
void FlexSramWrite(struct adapter * adapter, u32 bank, u32 addr, u8 *buf, u32 len)
{
    u32 i, command, retries;

    for ( i = 0; i < len; i++)
    {
	command = bank | addr | 0x04000000 | ( *buf << 0x10 );

        retries = 2;

        while ( ( ( ReadRegDW(adapter, 0x700) & 0x80000000 ) != 0 ) && ( retries > 0 ) )
	{
	    linuxdelayms(1);
	    retries--;
        };

	if ( retries == 0 ) printk("%s: SRAM timeout\n", __FUNCTION__);

	WriteRegDW(adapter, 0x700, command);
	
	buf++;
	addr++;
    }
}

//-------------------------------------------------------------------
void FlexSramRead(struct adapter * adapter, u32 bank, u32 addr, u8 *buf, u32 len)
{
    u32 i, command, value, retries;

    for ( i = 0; i < len; i++)
    {
	command = bank | addr | 0x04008000 ;

	retries = 10000;
	
	while ( ( ( ReadRegDW(adapter, 0x700) & 0x80000000 ) != 0 ) && ( retries > 0 ) )
	{
	    linuxdelayms(1);
	    retries--;
	};
	
	if ( retries == 0 ) printk("%s: SRAM timeout\n", __FUNCTION__);
		
	WriteRegDW(adapter, 0x700, command);

	retries = 10000;

	while ( ( ( ReadRegDW(adapter, 0x700) & 0x80000000 ) != 0 ) && ( retries > 0 ) )
	{
	    linuxdelayms(1);
	    retries--;