73x_dma.c

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/******************** (C) COPYRIGHT 2005 STMicroelectronics ********************
* File Name          : 73x_dma.c
* Author             : MCD Application Team
* Date First Issued  : 09/27/2005 :  V1.0
* Description        : This file provides all the DMA software functions.
**********************************************************************************
* History:
* 09/27/2005 :  V1.0
**********************************************************************************
* THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH
* CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME.
* AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT
* OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT
* OF SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION
* CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
*********************************************************************************/

/* Standard include ----------------------------------------------------------*/
#include "73x_dma.h"
#include "73x_cfg.h"

/* Include of other module interface headers ---------------------------------*/
/* Local includes ------------------------------------------------------------*/
/* Private typedef -----------------------------------------------------------*/
/* Private define ------------------------------------------------------------*/
/* Private macro -------------------------------------------------------------*/
/* Private variables ---------------------------------------------------------*/
/* Private function prototypes -----------------------------------------------*/
/* Interface functions -------------------------------------------------------*/
/* Private functions ---------------------------------------------------------*/
/*******************************************************************************
* Function Name  : DMA_DeInit
* Description    : Deinitializes the DMAx stream registers to their default reset
*                  values.
* Input          : - DMAx: where x can be 0, 1, 2  or 3 to select the DMA controller.
*                  - DMA_Stream: DMA stream to be deinitialized.
* Output         : None
* Return         : None
*******************************************************************************/
void DMA_DeInit(DMA_TypeDef* DMAx, u8 DMA_Stream)
{
  u32 Stream_BaseAddr = 0;
  
  /* get the base address of the stream to be used:
  Stream_BaseAddr := DMAx_Base + Stream offset */
  Stream_BaseAddr = (*(u32*)&(DMAx)) + DMA_Stream ;

  *(u16 *)(Stream_BaseAddr + DMA_SOURCEL) = 0;
  *(u16 *)(Stream_BaseAddr + DMA_SourceH) = 0;

  *(u16 *)(Stream_BaseAddr + DMA_DESTL) = 0;
  *(u16 *)(Stream_BaseAddr + DMA_DESTH) = 0;

  *(u16 *)(Stream_BaseAddr + DMA_MAX)  = 0;
  *(u16 *)(Stream_BaseAddr + DMA_CTRL) = 0;
  *(u16 *)(Stream_BaseAddr + DMA_LUBUFF) = 0;

  DMAx->MASK = 0;
  DMAx->CLR = 0;
  DMAx->Last = 0;
}

/*******************************************************************************
* Function Name  : DMA_Init
* Description    : Initializes the DMAx stream according to the specified
*                  parameters in the DMA_InitStruct structure.
* Input          : - DMAx: where x can be 0, 1, 2  or 3 to select the DMA controller.
*                  - DMA_InitStruct:  pointer to a DMA_InitTypeDef structure that
*                    contains the configuration information for the specified
*                    DMA stream.
* Output         : None
* Return         : None
******************************************************************************/
void DMA_Init(DMA_TypeDef* DMAx, DMA_InitTypeDef* DMA_InitStruct)
{
  u32 Stream_BaseAddr = 0;

  /* get the base address of the stream to be used:
     Stream_BaseAddr := DMAx_Base + Stream offset */
  Stream_BaseAddr = (*(u32*)&(DMAx)) + DMA_InitStruct->DMA_Stream ;

  *(u16 *)(Stream_BaseAddr + DMA_SOURCEL) = 0;
  *(u16 *)(Stream_BaseAddr + DMA_SourceH) = 0;

  *(u16 *)(Stream_BaseAddr + DMA_DESTL) = 0;
  *(u16 *)(Stream_BaseAddr + DMA_DESTH) = 0;

  *(u16 *)(Stream_BaseAddr + DMA_MAX)  = 0;
  *(u16 *)(Stream_BaseAddr + DMA_CTRL) = 0;

  /* set the buffer Size */
  *(u16 *)(Stream_BaseAddr + DMA_MAX) = DMA_InitStruct->DMA_BufferSize ;

  /* Fill the DMA Control Register */
  *(u16 *)(Stream_BaseAddr + DMA_CTRL) = DMA_InitStruct->DMA_SRC;
  *(u16 *)(Stream_BaseAddr + DMA_CTRL) |= DMA_InitStruct->DMA_DST;
  *(u16 *)(Stream_BaseAddr + DMA_CTRL) |= DMA_InitStruct->DMA_SRCSize;
  *(u16 *)(Stream_BaseAddr + DMA_CTRL) |= DMA_InitStruct->DMA_SRCBurst;
  *(u16 *)(Stream_BaseAddr + DMA_CTRL) |= DMA_InitStruct->DMA_DSTSize;
  *(u16 *)(Stream_BaseAddr + DMA_CTRL) |= DMA_InitStruct->DMA_Mode;
  *(u16 *)(Stream_BaseAddr + DMA_CTRL) |= DMA_InitStruct->DMA_Dir;
  
  if(DMA_InitStruct->DMA_Stream == DMA_Stream3)
  {
    *(u16 *)(Stream_BaseAddr + DMA_CTRL) |= DMA_InitStruct->DMA_M2M;
  }

  /* configure the Source base address */
  *(u16 *)(Stream_BaseAddr + DMA_SOURCEL) = DMA_InitStruct->DMA_SRCBaseAddr;
  *(u16 *)(Stream_BaseAddr + DMA_SourceH) = DMA_InitStruct->DMA_SRCBaseAddr >> 16;

  /* configure the Destination base address */
  *(u16 *)(Stream_BaseAddr + DMA_DESTL) = DMA_InitStruct->DMA_DSTBaseAddr;
  *(u16 *)(Stream_BaseAddr + DMA_DESTH) = DMA_InitStruct->DMA_DSTBaseAddr >> 16;
  
  switch(DMA_InitStruct->DMA_TriggeringSource)
  {
    case DMA_TriggeringSource_BSPI0 :
    CFG->R0 |= DMA_TriggeringSource_BSPI0;
    break;

    case DMA_TriggeringSource_BSPI1 :
    CFG->R0 |= DMA_TriggeringSource_BSPI1;
    break;

    case DMA_TriggeringSource_TIM8_TIM9:
    CFG->R0 &= DMA_TriggeringSource_TIM8_TIM9;
    break;
  }
}

/*******************************************************************************
* Function Name  : DMA_StructInit
* Description    : Fills in a DMA_InitTypeDef structure with the reset value of
*                  each parameter.
* Input          : DMA_InitStruct : pointer to a DMA_InitTypeDef structure
*                  which will be initialized.
* Output         : None
* Return         : None
*******************************************************************************/
void DMA_StructInit(DMA_InitTypeDef* DMA_InitStruct)
{
  /* initialize the DMA_BufferSize member */
  DMA_InitStruct->DMA_BufferSize = 0;

  /* initialize the DMA_SRCBaseAddr member */
  DMA_InitStruct->DMA_SRCBaseAddr = 0;

  /* initialize the DMA_DSTBaseAddr member */
  DMA_InitStruct ->DMA_DSTBaseAddr = 0;
  
  /* initialize the DMA_SRC member */
  DMA_InitStruct->DMA_SRC = DMA_SRC_NOT_INCR;
  
  /* initialize the DMA_DST member */
  DMA_InitStruct->DMA_DST = DMA_DST_NOT_INCR;
  
  /* initialize the DMA_SRCSize member */
  DMA_InitStruct->DMA_SRCSize = DMA_SRCSize_Byte;
  
  /* initialize the DMA_SRCBurst member */
  DMA_InitStruct->DMA_SRCBurst = DMA_SRCBurst_1Word;
  
  /* initialize the DMA_DSTSize member */
  DMA_InitStruct->DMA_DSTSize = DMA_DSTSize_Byte;
  
  /* initialize the DMA_Mode member */
  DMA_InitStruct->DMA_Mode = DMA_Mode_Normal;
  
  /* initialize the DMA_M2M member */
  DMA_InitStruct->DMA_M2M =  DMA_M2M_Disable;

  /* initialize the DMA_Dir member */
  DMA_InitStruct->DMA_Dir = DMA_Dir_PeriphSRC;
}

/*******************************************************************************
* Function Name  : DMA_AHBArbitrationConfig
* Description    : Handles the arbitration between CPU and  DMA on AHB bus.
* Input          : DMA_Priority : specifies the DMA priority on the AHB bus.
*                  This parameter can be one of the following values:
*                         - DMA_Priority_High: DMA has the highest priority.
*                         - DMA_Priority_Low: only CPU can access the bus.
* Output         : None
* Return         : None
*******************************************************************************/
void DMA_AHBArbitrationConfig(u8 DMA_Priority)
{
  if(DMA_Priority == DMA_Priority_High)
  {
    /* Switch-on Native Arbiter and AHB Arbiter clocks */
    CFG_PeripheralClockConfig(CFG_CLK_ARB, ENABLE);
    CFG_PeripheralClockConfig(CFG_CLK_AHB, ENABLE);

    /* set the DMA priority to the highest */
    ARB->PRIOR = DMA_Priority_High;
  }
  else
  {
    /* Switch-off the Native Arbiter and AHB Arbiter clocks */
    CFG_PeripheralClockConfig(CFG_CLK_ARB, DISABLE);
    CFG_PeripheralClockConfig(CFG_CLK_AHB, DISABLE);
  }
}

/*******************************************************************************
* Function Name  : DMA_Cmd
* Description    : Enables or disables the specified DMA stream.
* Input          : - DMAx: where x can be 0, 1, 2  or 3 to select the DMA controller.
*                  - DMA_Stream: specifies the DMA Stream to be enabled or
*                    disabled. This parameter can be one of the following values:
*                         - DMA_Stream0: use DMAx stream0.
*                         - DMA_Stream1: use DMAx stream1.
*                         - DMA_Stream2: use DMAx stream2.
*                         - DMA_Stream3: use DMAx stream3.
*                  - NewState: new state of the DMAx stream. This parameter can
*                  be: ENABLE or DISABLE.
* Output         : None
* Return         : None
*******************************************************************************/
void DMA_Cmd(DMA_TypeDef* DMAx, u8 DMA_Stream, FunctionalState NewState)
{
  u32 Stream_BaseAddr = 0;

 /* set the base address of the stream to be used:
    Stream_BaseAddr := DMAx_Base + Stream offset */
  Stream_BaseAddr = (*(u32*)&(DMAx)) + DMA_Stream ;

  if(NewState == ENABLE)
  {
    *(u16 *)(Stream_BaseAddr + DMA_CTRL) |= DMA_Enable;
  }
  else
  {
    *(u16 *)(Stream_BaseAddr + DMA_CTRL) &= DMA_Disable;
  }
}

/*******************************************************************************
* Function Name  : DMA_ITConfig
* Description    : Enables or disables the specified DMA interrupts.
* Input          : - DMAx: where x can be 0, 1, 2 or 3 to select the DMA controller.
*                  - DMA_IT: specifies the DMA interrupts sources to be enabled
*                    or disabled. This parameter can be any combination of the
*                    following values:
*                         - DMA_IT_SI0: Stream0 transfer end interrupt mask
*                         - DMA_IT_SI1: Stream1 transfer end interrupt mask
*                         - DMA_IT_SI2: Stream2 transfer end interrupt mask
*                         - DMA_IT_SI3: Stream3 transfer end interrupt mask