📄 adc.lst
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C51 COMPILER V7.50 ADC 08/20/2007 10:23:29 PAGE 1
C51 COMPILER V7.50, COMPILATION OF MODULE ADC
OBJECT MODULE PLACED IN adc.OBJ
COMPILER INVOKED BY: C:\Keil\C51\BIN\C51.EXE adc.c COMPACT OPTIMIZE(9,SIZE)
line level source
1 #include "Config.h"
2
3 #if defined( SUPPORT_PC ) || defined ( SUPPORT_DTV )
4
5 #include "reg.h"
6 #include "typedefs.h"
7 #include "i2c.h"
8 #include "adc.h"
9 #include "printf.h"
10 #include "main.h"
11 #include "tw88.h"
12 #include "pc_eep.h"
13 #include "measure.h"
14
15 // Address
16 #define PLLDIVM 0xc4
17 #define PLLDIVL 0xc5
18 #define PHASE 0xc7
19 #define RGB_SEL 0xd0
20 #define ADCMODE 0xc1
21 #define ADC_POWER 0xc3
22 #define VCOCURR 0xc6
23
24 //=============================================================================
25 // ADC Functions
26 //=============================================================================
27 CODE BYTE DTV_YPbPr_AD9883_init[] =
28 {
29 ADCI2CAddress, 51,
30
31 0xc5, 0xc1, // Sync control
32 0xc6, 0x26, // No Inversion/Csync from Sync slicer/SOG from SOYIN Pad/HPol=Neg/HSync=Composite Sync Separ
-ation input/LLPLL
33
34 0xc5, 0xcd, // Vsync Control
35 0xc6, 0x00, // Vsync: From Composite Sync Separation Output
36
37 0xc5, 0xd0, // Clamp Gain Control
38 0xc6, 0x00, // YUV
39
40 0xc5, 0xd1, // Clamp Mode Control
41 0xc6, 0x18, //
42
43 0xc5, 0xc8, // Hsync Output Width
44 0xc6, 0x20, //
45
46 0xc5, 0xd2, // Clamp Start Position
47 0xc6, 0x50, //
48
49 0xc5, 0xd3, // Clamp Stop Position
50 0xc6, 0x80, //
51
52 0xc5, 0xd5, // SOG Threshold
53 0xc6, 0x0f, //
54
C51 COMPILER V7.50 ADC 08/20/2007 10:23:29 PAGE 2
55 0xc5, 0xd6, // Pre-Coast
56 0xc6, 0x08, //
57
58 0xc5, 0xd7, // Post-Coast
59 0xc6, 0x08, //
60
61 //
62 0xc5, 0xe0, // Clamp Level Mode = Default Mode
63 0xc6, 0x03,
64
65 0xc5, 0xe1, // Y Programable Clamp Level
66 0xc6, 0x10,
67
68 0xc5, 0xe2, // UV Programable Clamp Level
69 0xc6, 0x80,
70
71 0xc5, 0xc3, // Power
72 0xc6, 0x03, // SOG On/PLL On
73
74 0xc5, 0xc9, // Gain 0x100
75 0xc6, 0x07,
76
77 0xc5, 0xca,
78 0xc6, 0x00,
79
80 0xc5, 0xcb,
81 0xc6, 0x00,
82
83 0xc5, 0xcc,
84 0xc6, 0x00,
85
86 0x33, 0x85,
87 0x38, 0x0e,
88 0x49, 0x30,
89 0x48, 0x4e,
90 0x47, 0x7e,
91 0x4a, 0x16,
92 0x4b, 0x16,
93 0x4d, 0x10,
94 0x4c, 0xe2,
95 0x40, 0x27,
96 0x41, 0x00,
97 0x42, 0x20,
98 0x44, 0x0b,
99
100 0xff, 0xff
101 };
102
103 CODE BYTE RGB_AD9883_init[] =
104 {
105 ADCI2CAddress, 52,
106
107 0xc5, 0xc1, // Sync control
108 0xc6, 0x38,
109 0xc5, 0xc3,
110 0xc6, 0x01,
111 0xc5, 0xcd, // Vsync Control
112 0xc6, 0x01, // Vsync: From Composite Sync Separation Output
113 0xc5, 0xd0, // Clamp Gain Control
114 0xc6, 0x08, // RGB
115 0xc5, 0xd1, // Clamp Mode Control
116 0xc6, 0x18, //
C51 COMPILER V7.50 ADC 08/20/2007 10:23:29 PAGE 3
117 0xc5, 0xc8, // Hsync Output Width
118 0xc6, 0x20, //
119 //
120 0xc5, 0xd2, // Clamp Start Position
121 0xc6, 0x50, //
122 0xc5, 0xd3, // Clamp Stop Position
123 0xc6, 0x80, //
124 0xc5, 0xd5, // SOG Threshold
125 0xc6, 0x04, //
126 0xc5, 0xd6, // Pre-Coast
127 0xc6, 0x00, //
128 0xc5, 0xd7, // Post-Coast
129 0xc6, 0x00, //
130
131 //
132 0xc5, 0xe0, // Clamp Level Mode = Default Mode
133 0xc6, 0x03,
134 0xc5, 0xe1, // Y Programable Clamp Level
135 0xc6, 0x10,
136 0xc5, 0xe2, // UV Programable Clamp Level
137 0xc6, 0x10,
138 0xc5, 0xc3, // Power
139 0xc6, 0x01, // SOG Off/PLL On
140 0xc5, 0xc9, // Gain 0x100
141 0xc6, 0x07,
142 //
143 0xc5, 0xca,
144 0xc6, 0x00,
145 0xc5, 0xcb,
146 0xc6, 0x00,
147 0xc5, 0xcc,
148 0xc6, 0x00,
149 // 0xc5, 0xc1, // Sync Control
150 // 0xc6, 0x20,
151 0x33, 0x05,
152 0x38, 0x0e,
153 0x49, 0x38,
154 0x48, 0x4b,
155 //
156 0x47, 0x79,
157 0x4a, 0x08,
158 0x4b, 0x08,
159 0x4d, 0x00,
160 0x4c, 0xf3,
161 0x40, 0x06,
162 0x41, 0x00,
163 0x42, 0x04,
164 0x44, 0x1f,
165
166 0x06, 0x08,
167 0xff, 0xff
168
169 };
170
171 void SetADCMode(BYTE mode)
172 {
173 1 #ifdef DEBUG_PC
dPuts("\r\n SetADCMode");
#endif
176 1
177 1 if( mode==DTV ) { // DTV-YPbPr
178 2 #ifdef DEBUG_PC
C51 COMPILER V7.50 ADC 08/20/2007 10:23:29 PAGE 4
dPuts(" -- Analog for SOG");
#endif
181 2 I2CDeviceInitialize( DTV_YPbPr_AD9883_init );
182 2 }
183 1 else { // RGB
184 2 #ifdef DEBUG_PC
dPuts(" -- Analog for HV");
#endif
187 2 I2CDeviceInitialize( RGB_AD9883_init );
188 2 }
189 1 }
190
191 WORD GetCoarse(void)
192 {
193 1 WORD buf;
194 1
195 1 buf = ReadADC(PLLDIVM) << 8;
196 1 buf |= ReadADC(PLLDIVL);
197 1
198 1 return buf;
199 1 }
200
201 void SetCoarse(WORD i)
202 {
203 1 #ifdef DEBUG_PC
dPrintf("\r\nSet Coarse->%04x(%d) ", i, i);
#endif
206 1
207 1 WriteADC(PLLDIVM, (BYTE)(i >> 8));
208 1 WriteADC(PLLDIVL, (BYTE)(i));
209 1 }
210
211 void SetPhase(BYTE j)
212 {
213 1 #ifdef DEBUG_PC
dPrintf("\r\nSet Phase->%04x ", (WORD)j);
#endif
216 1
217 1 WriteADC(PHASE, j&0x1f);
218 1 }
219
220 BYTE GetPhaseCurrent(void)
221 {
222 1 return ReadADC(PHASE) & 0x1f;
223 1 }
224
225 BYTE SetVCORange(DWORD _IPF)
226 {
227 1 BYTE VCO_CURR, oldv, chged=0;
228 1 BYTE val;
229 1
230 1 val = _IPF / 1000000L;
231 1
232 1 if ( val < 15 ) VCO_CURR = 0x01; // 00 001
233 1 else if( val < 34 ) VCO_CURR = 0x02; // 00 010
234 1 else if( val < 45 ) VCO_CURR = 0x0b; // 01 101
235 1 else if( val < 63 ) VCO_CURR = 0x0d; // 01 101
236 1 else if( val < 70 ) VCO_CURR = 0x0e; // 10 101
237 1 else if( val < 80 ) VCO_CURR = 0x14; // 10 100
238 1 else if( val <100 ) VCO_CURR = 0x16; // 10 101
239 1 else if( val <110 ) VCO_CURR = 0x16; // 10 110
240 1 else VCO_CURR = 0x1d; // 11 110
C51 COMPILER V7.50 ADC 08/20/2007 10:23:29 PAGE 5
241 1
242 1 oldv = ReadADC(VCOCURR) & 0x1f; // curr VCO_CURR value
243 1 val = VCO_CURR;
244 1 if( oldv != val ) {
245 2 chged = 1;
246 2 WriteADC(VCOCURR, val); //
247 2 delay(1); // time to stabilize
248 2 }
249 1
250 1 #ifdef DEBUG_PC
dPrintf("\r\nSetVCO=%02x, changed=%d", (WORD)val, (WORD)chged );
#endif
253 1
254 1 return chged;
255 1 }
256
257
258 #endif // SUPPORT_PC
259
260
MODULE INFORMATION: STATIC OVERLAYABLE
CODE SIZE = 268 ----
CONSTANT SIZE = 210 ----
XDATA SIZE = ---- ----
PDATA SIZE = ---- 10
DATA SIZE = ---- ----
IDATA SIZE = ---- ----
BIT SIZE = ---- ----
END OF MODULE INFORMATION.
C51 COMPILATION COMPLETE. 0 WARNING(S), 0 ERROR(S)
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