arm.v

来自「一个FPGA 测试例子,可以直接调试I/O口」· Verilog 代码 · 共 63 行

module arm(LnWE,LnOE,nGCS5,lIOW,lIOR,AEN,DIR,BOE,IOCHRDY,add0,add0_out);

input LnWE,LnOE,nGCS5,IOCHRDY,add0;
output lIOW,lIOR,AEN,DIR,BOE,add0_out;

reg lIOW,lIOR,AEN,DIR,BOE,add0_out;

parameter delay=100;

always @( nGCS5 or LnWE or LnOE)
begin

//lIOW
add0_out=add0;
lIOR = LnOE;
lIOW = LnWE;
AEN =  ~nGCS5;

if((~lIOW)&&(~nGCS5))
begin


 

BOE = 0;
//DIR = 1;
 DIR = 1;

end



else if((~lIOR)&&(~nGCS5))


begin

 DIR = 0 ;

 BOE = 0;


//BOE = 0;

end
else
begin
DIR = 1;
//BOE = 0;
BOE =1;
end




end



endmodule