ssd1928_1.0.txt

SSD1928英文数据手册

t11 D[15:0] delay for read 55 ns 
t12 D[15:0] hold for read 0 ns 

Note : Above timing is based on MCLK = 85MHz 

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11 APPLICATION EXAMPLES 

11.1 Application Diagram 
Figure 11-1 : Typical System Diagram (Generic #1 Bus) 
IOVDD 

CNF0CNF1 
CNF2 
AD_MODE 
COREVDD 
PVDD 
IOVDD 
LCD_DATA[7:0] 
LCD_FRAME 
LCD_LINE 
LCD_SHIFT 
LCD_DEN 
GPIO4 
M/R# 
CS# 
AB[18:1] 
DB[15:0] 
WE0# 
WE1# 
RD# 
RD/WR# 
CLKI2 
RESET# 
AB0 
Decoder 
SSD1928 
3.3V 
0.1μF 
0.1μF 
0.1μF 
IOVDD 4.7kΩ 
10kΩ 
10kΩ 
PLL_DIS 
1.8V 
4.7kΩ 
Generic #1 
BUS 

A[27:18] 

CSn# 

A[18:1] 

D[15:0] 

WE0# 
WE1# 
RD0# 

RD1# 

BUSCLK 
RESET# 

8-Bit 

CSTN 
LCD 


D[7:0] Display 

FRAME 

LINE 

Bias Power 

SHIFT 

MOD 


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Figure 11-2 : Typical System Diagram (Generic #2 Bus) 

Oscillator 
IOVDD 

Generic #2 
BUS 
e.g.LP22XX 

CLKI 
CNF0 
CNF1 
CNF2 
PLL_DIS 
AD_MODE 
FRAME 
LINE 
SHIFT 
DEN 
COREVDD 
PVDD 
IOVDD 
LCD_DATA[7:0] 
LCD_FRAME 
LCD_LINE 
LCD_SHIFT 
LCD_DEN 
GPIO4 
RD/WR# 
M/R# 
CS# 
AB[18:1] 
DB[15:0] 
AB0 
WE0# 
WE1# 
RD# 
RESET# 
Decoder 
SSD1928 
3.3V 
0.1μF 
0.1μF 
0.1μF 
IOVDD 
10kΩ 
4.7kΩ 
4.7kΩ 
1.8V 
4.7kΩ 
A[27:18] 

CSn# 

A[18:1] 

D[15:0] 
BLS0# 
WE# 
BLS1# 

OE# 

RESET# 

8-Bit 
TFT 

Display 

D[7:0] 

Bias Power 


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Figure 11-3 : Typical System Diagram (Indirect 8080 16 bit Bus) 


8080 1.8V 

8-Bit 

CSn# 

CLKI 
CNF0CNF1CNF2 
PLL_DIS 
AD_MODE 
Bias Power 
D[7:0] 
FRAME 
LINE 
SHIFT 
DEN 
COREVDD 
PVDD 
IOVDD 
LCD_DATA[7:0] 
LCD_FRAME 
LCD_LINE 
LCD_SHIFT 
LCD_DEN 
GPIO4 
CS# 
AB[3] 
DB[15:0] 
WE0# 
RD# 
RESET# 
Oscillator 
SSD1928 
3.3V 
0.1μF 
0.1μF 
IOVDD 
10kΩ 
4.7kΩ 
TFT 
Display 


ALE 


D[15:0] 
WE# 
RD# 



RESET# 
0.1μF 


All un-used MCU interface pins 
(AB18-4, AB2-0, WE1#, RD/WR#, 
M/R#) should tied to IOVSS 


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12 Pseudo-code Examples for Indirect address mode 

12.1 8080 Indirect address mode 
For example, PORTA is used for control signals and PORTB is used for data signals. 
PORTA[3:0] are the control signals 

PORTA[7] PORTA[6] PORTA[5] PORTA[4] PORTA[3] PORTA[2] PORTA[1] PORTA[0] 
X X X X CS# RD# WR# D/C# 

X : Don’t care 
PORTB[15:0] are the data signals for 16 bit mode 
PORTB[7:0] are the data signals for 8 bit mode 

read_command (cmd) 
write PORTA, 0x0A [CS#=1, RD#=0, WR#=1, D/C#=0] 
write PORTA, 0x02 [CS#=0, RD#=0, WR#=1, D/C#=0] 
read PORTB, cmd 
write PORTA, 0x0E [CS#=1, RD#=1, WR#=1, D/C#=0] 
read_data (data) 
write PORTA, 0x0B [CS#=1, RD#=0, WR#=1, D/C#=1] 
write PORTA, 0x03 [CS#=0, RD#=0, WR#=1, D/C#=1] 
read PORTB, data 
write PORTA, 0x0F [CS#=1, RD#=1, WR#=1, D/C#=1] 
write_command (cmd) 
write PORTB, cmd 
write PORTA, 0x0C [CS#=1, RD#=1, WR#=0, D/C#=0] 
write PORTA, 0x04 [CS#=0, RD#=1, WR#=0, D/C#=0] 
write PORTA, 0x0E [CS#=1, RD#=1, WR#=1, D/C#=0] 
write_data (data) 
write PORTB, data 
write PORTA, 0x0D [CS#=1, RD#=1, WR#=0, D/C#=1] 
write PORTA, 0x05 [CS#=0, RD#=1, WR#=0, D/C#=1] 
write PORTA, 0x0F [CS#=1, RD#=1, WR#=1, D/C#=1] 

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Example 1 : Register Access with 16 bit indirect address mode (Big Endian, CNF4=1) with Word Mode 

(Write Register REG[0x010h]=0x11, REG[0x011h]=0x22, REG[0x012h]=0x33, REG[0x013h]=0x04 and read 
back the contents) 

Step 1: Set the start address to 0x00010 and write DATA0 
write_command 0x0000 [M/R#=0 => Register] 
write_command 0x1001 [start address = 0x00010, MODE_SL=0x01 => Word] 
write_data 0x1122 [write word 0x1122 to REG[0x010]] 

Step 2 : Write DATA1 
write_data 0x3304 [write word 0x3304 to REG[0x012]] 

Step 3 : Set the start Address to 0x00010 and dummy read 
write_command 0x0000 [M/R#=0 => Register] 
write_command 0x1001 [start address = 0x00010,MODE_SL=0x01 => Word] 
read_data DUMMY [first read cycle is dummy] 

Step 4 : Read Back the Data [Total = 4 bytes] 
read_data DATA0 [read back value is 0x1122 => REG[0x010]=0x1122] 
read_data DATA1 [read back value is 0x3304 => REG[0x012]=0x3304] 

Example 2 : Register Access with 16 bit indirect address mode (Big Endian, CNF4=1) with Byte Mode 

(Write Register REG[0x010h]=0x11, REG[0x011h]=0x22, REG[0x012h]=0x33, REG[0x013h]=0x04 and read 
back the contents) 

Step 1: Set the start address to 0x00010 and write DATA0 
write_command 0x0000 [M/R#=0 => Register] 
write_command 0x1000 [start address = 0x00010, MODE_SL=0x00 => Byte] 
write_data 0x1122 [write word 0x11 to REG[0x010]] 


Step 2 : Write the DATA1-3 
write_data 0x3344 [write word 0x44 to REG[0x011]] 
write_data 0xAABB [write word 0xAA to REG[0x012]] 
write_data 0xCC07 [write word 0x07 to REG[0x013]] 


Step 3 : Set the start Address to 0x00010 and dummy read 
write_command 0x0000 [M/R#=0 => Register] 
write_command 0x1000 [start address = 0x00010,MODE_SL=0x00 => Byte] 
read_data DUMMY [first read cycle is dummy] 


Step 4 : Read Back the Data [Total = 4 bytes] 
read_data DATA0 [read back value is 0x1144 => REG[0x010]=0x11] 
read_data DATA1 [read back value is 0x1144 => REG[0x011]=0x44] 
read_data DATA2 [read back value is 0xAA07 => REG[0x012]=0xAA] 
read_data DATA3 [read back value is 0xAA07 => REG[0x013]=0x07] 


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Example 3 : Memory Access with 16 bit indirect address mode (Big Endian, CNF4=1) with Word Mode 

(Write Memory AB[0x00910h]=0x11, AB[0x00911h]=0x22, AB[0x00912h]=0x33, AB[0x00913h]=0x44 and read 
back the contents) 

Step 1: Set the start address to 0x00910 and write DATA0 
write_command 0x8009 [M/R#=1 => Memory] 
write_command 0x1001 [start address = 0x00910, MODE_SL=0x01 => Word] 
write_data 0x1122 [write word 0x1122 to 0x00910] 

Step 2 : Write the DATA1 
write_data 0x3344 [write word 0x3344 to 0x00912] 

Step 3 : Set the start Address to 0x00910 and dummy read 
write_command 0x8009 [M/R#=1 => Memory] 
write_command 0x1001 [start address = 0x00910,MODE_SL=0x01 => Word] 
read_data DUMMY [first read cycle is dummy] 

Step 4 : Read Back the Data [Total = 4 bytes] 
read_data DATA0 [read back value is 0x1122 => AB[0x00910]=0x1122] 
read_data DATA1 [read back value is 0x3344 => AB[0x00912]=0x3344] 

Example 4 : Memory Access with 16 bit indirect address mode (Big Endian, CNF4=1) with Byte Mode 

(Write Memory AB[0x00910h]=0x11, AB[0x00911h]=0x22, AB[0x00912h]=0x33, AB[0x00913h]=0x44 and read 
back the contents) 

Step 1: Set the start address to 0x00910 and write DATA0 
write_command 0x8009 [M/R#=1 => Memory] 
write_command 0x1000 [start address = 0x00910, MODE_SL=0x00 => Byte] 
write_data 0x1122 [write word 0x11 to AB[0x00910]] 


Step 2 : Write the DATA1-3 
write_data 0x3344 [write word 0x44 to AB[0x00911]] 
write_data 0xAABB [write word 0xAA to AB[0x00912]] 
write_data 0xCCDD [write word 0xDD to AB[0x00913]] 


Step 3 : Set the start Address to 0x00910 and dummy read 
write_command 0x8009 [M/R#=1 => Memory] 
write_command 0x1000 [start address = 0x00910,MODE_SL=0x00 => Byte] 
read_data DUMMY [first read cycle is dummy] 


Step 4 : Read Back the Data [Total = 4 bytes] 
read_data DATA0 [read back value is 0x1144 => AB[0x00910]=0x11] 
read_data DATA1 [read back value is 0x1144 => AB[0x00911]=0x44] 
read_data DATA2 [read back value is 0xAADD => AB[0x00912]=0xAA] 
read_data DATA3 [read back value is 0xAADD => AB[0x00913]=0xDD] 


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Example 5 : Register Access with 8 bit indirect address mode (Big Endian, CNF4=1) 

(Write Register REG[0x010h]=0x11, REG[0x011h]=0x22, REG[0x012h]=0x33, REG[0x013h]=0x04 and read 
back the contents) 

Step 1: Set the start address to 0x00010 and write DATA0 
write_command 0x00 [M/R#=0 => Register] 
write_command 0x00 
write_command 0x10 [start address = 0x00010] 
write_data 0x11 [write word 0x11 to REG[0x010]] 

Step 2 : Write the DATA1-3 
write_data 0x22 [write word 0x22 to REG[0x011]] 
write_data 0x33 [write word 0x33 to REG[0x012]] 
write_data 0x04 [write word 0x04 to REG[0x013]] 

Step 3 : Set the start Address to 0x00010 and dummy read 
write_command 0x00 [M/R#=0 => Register] 
write_command 0x00 
write_command 0x10 [start address = 0x00010] 
read_data DUMMY [first read cycle is dummy] 

Step 4 : Read Back the Data [Total = 4 bytes] 
read_data DATA0 [read back value is 0x11 => REG[0x010]=0x11] 
read_data DATA1 [read back value is 0x22 => REG[0x011]=0x22] 
read_data DATA2 [read back value is 0x33 => REG[0x012]=0x33] 
read_data DATA3 [read back value is 0x04 => REG[0x013]=0x04] 

SSD1928 Rev 1.0 P 43/46 Mar 2007 Solomon Systech 

Example 6 : Memory Access with 8 bit indirect address mode (Big Endian, CNF4=1) 

(Write Memory AB[0x00910h]=0x11, AB[0x00911h]=0x22, AB[0x00912h]=0x33, AB[0x00913h]=0x44 and read 
back the contents) 

Step 1: Set the start address to 0x00910 and write DATA0 
write_command 0x80 [M/R#=1 => Memory] 
write_command 0x09 
wri