ssd1928_1.0.txt

SSD1928英文数据手册

D/C# 

DB7:0 

write M/R# 
AB18:16(note 1) 
write 
AB7:0 
write 
DATA[N] 
write 
DATA[N+2] 
write 
DATA[N+1] 
write 
AB15:8 
write 
DATA[N+n] 
Setup start address 
Write data 

Figure 7-6 : 8080 8 bit Interface Timing (write cycle) 

Solomon Systech Mar 2007 P 26/46 Rev 1.0 SSD1928 
Note : 

1 
: 
Bit7 represent the M/R#, Bit7 = 1 means memory access, Bit7 = 0 means register access.
Bit6:3 = 0.
Bit2:0 represent the the address AB18:16. 
7 MCLK is needed for each cycle if WAIT# is not used for interface. *

Figure 7-7 : 8080 8 bit Interface Timing (read cycle) 

SSD1928 Rev 1.0 P 27/46 Mar 2007 Solomon Systech 
CS# 

RD#

WR#

D/C# 

DB7:0 

write M/R# 
AB18:16 
(note 1) 
write 
AB7:0 
readDATA[N+1] 
Write 
0x00 
readDATA[N+n-
1] 
write 
AB15:8 
INVALID(note 2) 
readDATA[N+n] 
readDATA[N] 
Write 
0x00 
Write 
0x00
Read Burst Termination 

Setup start address Read data 
(note 3) 

Note : 

1 
: 
Bit7 represent the M/R#, Bit7 = 1 means memory access, Bit7 = 0 means register access.
Bit6:3 = 0.
Bit2:0 represent the the address AB18:16.
2 
: 
Invalid dummy read cycle is needed after address is written.
3 
: 
Read Burst Termination must be assertesd for all JPEG relaeted memory access. 
7 MCLK is needed for each cycle if WAIT# is not used for interface. *

7.4 Registers 
It stores all the register settings for different functional modules. Refer to Application Note for Register Table. 

7.5 JPEG Encoder/Decoder 
The JPEG codec can compress the image from CMOS camera to JPEG format and store to embedded memory. 
With help of MMC/SD card interface, the data can be stored in external MMC/SD card. Also, the codec can 
decompress the JPEG image from embedded memory to display(1) . If the image stored in MMC/SD card is 
copied to embedded memory, the JPEG codec can decompress it to display also. 

Note 

(1) If the output memory address is the same as the overlay window, the decompressed image will be display 
immediately. 
7.6 Image Capture Interface 
The image capture interface can connect to a CMOS camera of resolution up to 1600 x 1200 (2.0 MegaPixel) or 
video source. The image is captured into the embedded memory. If the image capture is continuous, and the 
destination is the overlay window starting address, a preview window will be created. Since the CMOS camera 
resolution should be far higher than the display panel. 

7.7 2D Engine 
The 2D engine is designed on the basis of Microsoft Windows GDI. It support straight line drawing, rectangle 
drawing, rectangle color fill, rectangle pattern fill, BitBLT, color expansion, StretchBLT and alpha blending. 

7.8 Display Interface 
This is LCD interface for the main display. The maximum resolution of the LCD depends on the size of frame 
buffer located in the embedded memory. This display interface supports most panel type, including dump STN, 
CSTN, TFT. The smart STN, CSTN, TFT, OLED panel of parallel and serial interface are also supported. 

7.9 MMC/SD/SDIO Interface 
This interface act as a bridge between the MCU and the external memory card. This interface can also used as a 
bridge between the internal functional blocks such as JPEG encoder/decoder and external memory card. Since 
this interface also supports SDIO, the MCU can use this interface as an expansion slot. 

7.10 General Purpose Input/Output (GPIO) 
This is a collection of 5 GPIOs with can be used for LCD, keypad, LED backlight control and so on. 

Solomon Systech Mar 2007 P 28/46 Rev 1.0 SSD1928 

MAXIMUM RATINGS 

Table 8-1: Absolute Maximum Ratings 

Symbol Parameter Rating Units 
IOVDD Supply Voltage VSS - 0.3 to 4.0 V 
VIN Input Voltage VSS - 0.3 to 5.0 V 
VOUT Output Voltage VSS - 0.3 to IOVDD + 0.5 V 
TSTG Storage Temperature -65 to 150 °C 
TSOL Solder Temperature/Time 260 for 10 sec. max at lead °C 

Maximum Ratings are those values beyond which damage to the device may occur. Functional operation should be 
restricted to the limits in the Electrical Characteristics tables or Pin Description section. 

This device contains circuitry to protect the inputs against damage due to high static voltages or electric fields; however, it is 
advised that normal precautions to be taken to avoid application of any voltage higher than maximum rated voltages to this 
high impedance circuit. For proper operation it is recommended that VIN and VOUT be constrained to the range VSS ≤ (VIN or 
VOUT) ≤ IOVDD. Reliability of operation is enhanced if unused input are connected to an appropriate logic voltage level (e.g., 
either VSS or IOVDD). This device is not radiation protected. 

Table 8-2 : Recommended Operating Conditions 

Symbol Parameter Condition Min Typ Max Units 
IOVDD Supply Voltage VSS = 0V 3.0 3.3 3.6 V 
COREVDD Supply Voltage VSS = 0V 1.62 1.8 1.98 V 
PVDD Supply Voltage VSS = 0V 1.62 1.8 1.98 V 
VIN Input Voltage VSS IOVDD V 
TOPR Operating Temperature -30 25 85 °C 

SSD1928 Rev 1.0 P 29/46 Mar 2007 Solomon Systech 

DC CHARACTERISTICS 
Table 9-1 : Electrical Characteristics for IOVDD = 3.3V typical 

Symbol Parameter Condition Min Typ Max Units 
PSTY Quiescent Power Quiescent Conditions 700 μW 
PLL_DIS = VSS 
IIZ Input Leakage Current -1 1 μA 
IOZ Output Leakage Current -1 1 μA 
VOH High Level Output Voltage IOVDD = min 
IOH = -2mA (Type 1) 
-4mA (Type 2) 
-16mA (Type 3) 
70% * 
IOVDD 
V 
VOL Low Level Output Voltage IOVDD = min 
IOL = 2mA (Type 1) 
4mA (Type 2) 
16mA (Type 3) 
30% * 
IOVDD 
V 
VIH High Level Input Voltage LVTTL Level, IOVDD = 90% * V 
max IOVDD 
VIL Low Level Input Voltage LVTTL Level, IOVDD = 
min 
10% * 
IOVDD 
V 
VT+ High Level Input Voltage LVTTL Schmitt 1.1 V 

Solomon Systech Mar 2007 P 30/46 Rev 1.0 SSD1928 


10 AC CHARACTERISTICS 

Conditions: 
IOVDD = 3.3V ± 10% 
TA = -30°C to 85°C 
Trise and Tfall for all inputs must be < 5 ns (10% ~ 90%) 
CL = 50pF (Bus/CPU Interface) 
CL = 0pF (LCD Panel Interface) 

10.1 Clock Timing 
10.1.1 Input Clocks 
Table 10-1 : Clock Input Requirements for CLKI 

Symbol Parameter Min Max Units 
FCLKI Input Clock Frequency (CLKI) 2 4 MHz 
TCLKI Input Clock period (CLKI) 1/fCLKI ns 

Table 10-2 : Oscillator Clock Input Requirements for CLKI2 

Symbol Parameter Min Max Units 
FCLKI2 Input Clock Frequency (CLKI2) 85 MHz 
TCLKI2 Input Clock period (CLKI2) 1/fCLKI2 ns 

SSD1928 Rev 1.0 P 31/46 Mar 2007 Solomon Systech 

10.2 CPU Interface Timing 
The following section are CPU interface AC Timing based on IOVDD = 3.3V. 

10.2.1 Generic #1 Interface Timing 
t13 
t7 
t9 
A[18:1], 
M/R#, 
t10 
CLK 
WAIT# 
RD0#, RD1# 
WE0#, WE1# 
CS# 
D[15:0] 
(read) 
D[15:0] 
(write) 
TCLK t2t1 
t3 t4 
t6t5 
t15 
t11 
t14 
t12 
t8 
VALID 
Figure 10-1 : Generic #1 Interface Timing 

Solomon Systech Mar 2007 P 32/46 Rev 1.0 SSD1928 

Table 10-3 : Generic #1 Interface Timing 

Symbol Parameter Min Max Units 
fCLK Bus Clock frequency 85 MHz 
TCLK Bus Clock period 1/fCLK ns 
t1 Clock pulse width high 6 ns 
t2 Clock pulse width low 6 ns 
t3 A[18:1], M/R# setup to first CLK rising edge where CS# = 0 and 
either RD0#, RD1# = 0 or WE0#, WE1# = 0 
1 ns 
t4 A[18:1], M/R# hold from either RD0#, RD1# or WE0#, WE1# rising 
edge 
0 ns 
t5 CS# setup to CLK rising edge 1 ns 
t6 CS# hold from either RD0#, RD1# or WE0#, WE1# rising edge 1 ns 
t7a RD0#, RD1#, WE0#, WE1# asserted for MCLK = PLL_CLK 13 TCLK 
t7b RD0#, RD1#, WE0#, WE1# asserted for MCLK = PLL_CLK ÷2 18 TCLK 
t7c RD0#, RD1#, WE0#, WE1# asserted for MCLK = PLL_CLK ÷3 23 TCLK 
t7d RD0#, RD1#, WE0#, WE1# asserted for MCLK = PLL_CLK ÷4 28 TCLK 
t8 RD0#, RD1#, WE0#, WE1# setup to CLK rising edge 1 ns 
t9 Falling edge of either RD0#, RD1# or WE0#, WE1# to WAIT# 
driven low 
3 15 ns 
t10 Rising edge of either RD0#, RD1# or WE0#, WE1# to WAIT# 
high impedance 
3 13 ns 
t11 D[15:0] setup to third CLK rising edge where CS# = 0 and 
WE0#,WE1#=0 (write cycle)(see note 1) 
0 ns 
t12 D[15:0] hold from WAIT# rising edge (write cycle) 0 ns 
t13 RD0#, RD1# falling edge to D[15:0] driven (read cycle) 3 14 ns 
t14 WAIT# rising edge to D[15:0] valid (read cycle) 2 ns 
t15 RD0#, RD1# rising edge to D[15:0] high impedance (read cycle) 3 11 ns 

1. t11 is the delay from when data is placed on the bus until the data is latched into the write buffer. 
SSD1928 Rev 1.0 P 33/46 Mar 2007 Solomon Systech 

10.2.2 Generic #2 Interface Timing (e.g. ISA) 
t13 
t7 
t9 
SA[18:0], 
M/R#, SBHE# 
t10 
BUSCLK 
IOCHRDY 
MEMR# 
MEMW# 
CS# 
SD[15:0] 
(read) 
SD[15:0] 
(write) 
TBUSCLK t2t1 
t3 t4 
t6t5 
t15 
t11 
t14 
t12 
t8 
VALID 
Figure 10-2 : Generic #2 Interface Timing 

Solomon Systech Mar 2007 P 34/46 Rev 1.0 SSD1928 

Table 10-4 : Generic #2 Interface Timing 

Symbol Parameter Min Max Units 
fBUSCLK Bus Clock frequency 85 MHz 
TBUSCLK Bus Clock period 1/fBUSCLK ns 
t1 Clock pulse width high 6 ns 
t2 Clock pulse width low 6 ns 
t3 SA[18:0], M/R#, SBHE# setup to first BUSCLK rising edge where 
CS# = 0 and either MEMR# = 0 or MEMW# = 0 
1 ns 
t4 SA[18:0], M/R#, SBHE# hold from either MEMR# or MEMW# 
rising edge 
0 ns 
t5 CS# setup to BUSCLK rising edge 1 ns 
t6 CS# hold from either MEMR# or MEMW# rising edge 0 ns 
t7a MEMR# or MEMW# asserted for MCLK = PLL_CLK 13 TBUSCLK 
t7b MEMR# or MEMW# asserted for MCLK = PLL_CLK ÷2 18 TBUSCLK 
t7c MEMR# or MEMW# asserted for MCLK = PLL_CLK ÷3 23 TBUSCLK 
t7d MEMR# or MEMW# asserted for MCLK = PLL_CLK ÷4 28 TBUSCLK 
t8 MEMR# or MEMW# setup to BUSCLK rising edge 1 ns 
t9 Falling edge of either MEMR# or MEMW# to IOCHRDY driven low 3 15 ns 
t10 Rising edge of either MEMR# or MEMW# to IOCHRDY high 
impedance 
3 13 ns 
t11 SD[15:0] setup to third BUSCLK rising edge where CS# = 0 and 
MEMW#=0 (write cycle)(see note1) 
0 ns 
t12 SD[15:0] hold from IOCHRDY rising edge (write cycle) 0 ns 
t13 MEMR# falling edge to SD[15:0] driven (read cycle) 3 13 ns 
t14 IOCHRDY rising edge to SD[15:0] valid (read cycle) 2 ns 
t15 Rising edge of MEMR# to SD[15:0] high impedance (read cycle) 3 12 ns 

1. t11 is the delay from when data is placed on the bus until the data is latched into the write buffer. 
SSD1928 Rev 1.0 P 35/46 Mar 2007 Solomon Systech 

10.2.3 8080 Indirect Interface Timing 
t7

 t8 


D/C# 

CS# 

WR# 
(write) 

RD# 
(read) 


D[15:0] 
(write) 
Hi-Z 


D[15:0] 
(read) 



t1 

t2 


t5 

t6 


t4

t3 


t9 

t10 


t12

t11 


VALID 


Hi-Z 

Figure 10-3 : 8080 Interface Timing 
Table 10-5 : 8080 Interface Timing 


Symbol Parameter Min Max Units 
t1 CS# pulse width low 82 ns 
t2 CS# pulse width high 82 ns 
t3 RD# setup 18 ns 
t4 RD# hold 0 ns 
t5 WR# setup 18 ns 
t6 WR# hold 0 ns 
t7 D/C# setup 18 ns 
t8 D/C# hold 0 ns 
t9 D[15:0] setup for write 18 ns 
t10 D[15:0] hold for write 0 ns