ssd1928_1.0.txt

SSD1928英文数据手册

Pin Name Type 
LQF 
P Pin 
# 
Cell RESET# 
State Description 
SD_CLK O 75 LO3 0 SD clock 
SD_CMD IO 74 LB2 -SD command 
SD_DATA[3:0] IO 67-70 LB2 -SD data[3:0] 
SD_DATA[3:1] are not used for 1 bit SD or MMC 
SD_CD I 71 LIS -SD card inserted 
SD_WP I 76 LIS -SD card write protected 

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6.6 Configuration 
Table 6-6 : Configuration Pin Descriptions 

Pin Name Type LQFP 
Pin # Cell RESET 
# State Description 
CNF[6,4:0 
], 
AD_MOD 
E 
I 77-83 LIS — 
These inputs are used to configure the SSD1928 – see 
Table 6-9 : Summary of Configuration pins. 
Note 
(1) These pins are used for configuration of the 
SSD1928 and must be connected directly to IOVDD or 
VSS. 

6.7 Miscellaneous 
Table 6-7 : Miscellaneous Pin Descriptions 

Pin Name Type LQFP 
Pin # Cell RESET 
# State Description 
GPIO[4:0] IO 92-96 LB3 0 
General Purpose IO. Those GPIO signals can be 
programmed as LCD control which sync with LCD 
signals. 
TESTO O 43 LO3 0 Test output pin. Floated this pin in normal operation. 

6.8 Power and Ground 
Table 6-8 : Power and Ground Pin Descriptions 

Pin Name Type LQFP 
Pin # Cell RESET 
# State Description 
IOVDD P 
18, 48, 
90, 
104, 
114 
P — 
3.3V Power supply pins for I/O pads. 
It is recommended to place a 0.1μF bypass 
capacitor close to each of these pins. 
IOVSS P 17, 49, 
91, 103 P — Ground pins for I/O pads 
COREVDD P 
5, 27, 
56, 73, 
89, 
101, 
112 
P — 
1.8V Power supply pins for core. 
It is recommended to place a 0.1μF bypass 
capacitor close to each of these pins. 
COREVSS P 
6, 28, 
38, 55, 
72, 88, 
102, 
111 
P — Ground pins for core 
PVDD P 34 P — 
1.8V Power supply pins for PLL. 
It is recommended to place a 0.1μF bypass 
capacitor close to each of these pins. 
PVSS P 35 P — Ground pins for PLL 

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6.9 Summary of Configuration 
These pins are used for configuration of the SSD1928 and must be connected directly to IOVDD or IOVSS. 
The state of AD_MODE, CNF[6, 4:0] is latched on the rising edge of RESET# or after the software reset 
function is activated (REG[A2h] bit 0). Changing state at any other time has no effect. 

Table 6-9 : Summary of Configuration pins 

SSD1928 Power-On/Reset State 
Configuration 
Input 1 (Connected to IOVDD) 0 (Connected to IOVSS) 
Select host bus interface as follows: 
AD_MODE CNF2 CNF1 CNF0 Host Bus 
0 0 1 1 Generic#1 
0 1 0 0 Generic#2 
CNF[2:0], AD_MODE 1 0 1 1 Indirect 8 bit 8080 (For Big Endian only) 
1 1 0 0 Indirect 16 bit 8080 
Note : 
The host bus interface is 18-bit only. 
CNF3 Configure GPIO pins as inputs at Configure GPIO pins as outputs at power-on 
power-on 
CNF4 Big Endian bus interface Little Endian bus interface 
CNF6 MCLK = PLL_CLK / 4 MCLK = PLL_CLK 
Note : 
Recommended to use CNF6 = 0 for Indirect addressing mode 

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6.10 Host Bus Interface Pin Mapping 
Table 6-10 : Host Bus Interface Pin Mapping 
SSD1928 Pin 
Name Generic #1 Generic #2 Indirect 8080 
AB0 Connected to IOVSS A0 Connected to IOVSS 
AB[18:4, 2, 1] A[18:4, 2, 1] Connected to IOVSS 
AB[3] A[3] D/C# 
DB[15:0] D[15:0] D[15:0] 
CS# External Decode 
M/R# External Decode Connected to IOVSS 
CLKI2 
(optional) BUSCLK 
RD/WR# RD1# Connected to IOVDD Connected to VSS 
RD# RD0# RD# RD# 
WE0# WE0# WE# WR# 
WE1# WE1# BHE# Connected to IOVSS 
RESET# RESET# 

6.11 LCD Interface Pin Mapping 
Table 6-11 : LCD Interface Pin Mapping 
Pin Names DUMB DRIVER SMART DRIVER 
Mono STN CSTN TFT TFT CSTN OLED TFT(Hitachi) 
4-bit 8-bit 4-bit 8-bit Serial 8 
bit 8/9-bit /3/4 wire 
LCD_FRAME FRAME Drive 0 Drive 0 Drive 0 Drive 0 
LCD_LINE LINE Drive 0 Drive 0 Drive 0 Drive 0 
LCD_SHIFT SHIFT Drive 0 Drive 0 Drive 0 Drive 0 
LCD_DEN MOD DEN Drive 0 Drive 0 Drive 0 Drive 0 
LCD_DATA0 Drive 0 D0 Drive 0 D0(B5) 1 D0 D0 D0/SDA 
LCD_DATA1 Drive 0 D1 Drive 0 D1(R5) 1 D1 D1 
LCD_DATA2 Drive 0 D2 Drive 0 D2(G4) 1 D2 D2 
LCD_DATA3 Drive 0 D3 Drive 0 D3(B31 D3 D3 
LCD_DATA4 D0 D4 D0(R2)1 D4(R3) 1 D4 D4 
LCD_DATA5 D1 D5 D1(B1)1 D5(G2) 1 D5 D5 
LCD_DATA6 D2 D6 D2(G1)1 D6(B1) 1 D6 D6/SCK D6 
LCD_DATA7 D3 D7 D3(R1)1 D7(R1) 1 D7 D7/SDA D7 
LCD_D/C# Drive 0 Drive 0 Drive 0 Drive 0 Drive 0 D/C# 
LCD_CS# Drive 0 Drive 0 Drive 0 Drive 0 Drive 0 CS# 
LCD_WR#;LCD 
_RD/WR# 
Drive 0 Drive 0 Drive 0 Drive 0 Drive 0 WR#;R/W# WR#;E;SCK 
LCD_RD#; 
LCD_E 
Drive 0 Drive 0 Drive 0 Drive 0 Drive 0 RD#;E RD#;R/W# 

Note 

(1) These pin mappings use signal names commonly used for each panel type, however signal names may differ 
between panel manufacturers. The values shown in brackets represent the color components as mapped to the 
corresponding LCD_DATAxx signals at the first valid edge of LCD_SHIFT. 
6.12 Data Bus Organization 
There are two data bus architectures, little endian and big endian. Little endian means the bytes at lower 
addresses have lower significance. Big endian means the most significant byte has the lowest address. 

Table 6-12 : Data Bus Organization 

D[15:8] D[7:0] 
Big endian 2N 2N + 1 

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Little endian 2N + 1 2N 
Note 

(1) N : Byte Address 
Table 6-13 : Pin State Summary 

MCU Mode (Endian) A0 RD/WR# RD# WE1# WE0# Operation 
Generic#1 (Big) X 0 0 1 1 Word read 
X 0 1 1 1 High byte read 2N 
X 1 0 1 1 Low byte read 2N+1 
X 1 1 0 0 Word write 
X 1 1 0 1 High byte write 2N 
X 1 1 1 0 Low byte write 2N+1 
Generic#1 (Little) X 0 0 1 1 Word read 
X 0 1 1 1 High byte read 2N+1 
X 1 0 1 1 Low byte read 2N 
X 1 1 0 0 Word write 
X 1 1 0 1 High byte write 2N+1 
X 1 1 1 0 Low byte write 2N 
Generic#2 (Big) 0 X 0 0 1 Word read 
0 X 0 1 1 High byte read 2N 
1 X 0 0 1 Low byte read 2N+1 
0 X 1 0 0 Word write 
0 X 1 1 0 High byte write 2N 
1 X 1 0 0 Low byte write 2N+1 
Generic#2 (Little) 0 X 0 0 1 Word read 
1 X 0 0 1 High byte read 2N+1 
0 X 0 1 1 Low byte read 2N 
0 X 1 0 0 Word write 
1 X 1 0 0 High byte write 2N+1 
0 X 1 1 0 Low byte write 2N 

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7 FUNCTIONAL BLOCK DESCRIPTIONS 

7.1 Phase Lock Loop (PLL) 
The built-in PLL synthesize the internal clock by an external 2MHz – 4MHz clock through the CLKI and CLKO. 
RC circuit should be connected if internal PLL is selected. The input of clock source can be either oscillator or 
crystal. If oscillator is used, the clock source is input directly to CLKI and leave CLKO floating. The target 
maximum output frequency of the PLL is 85MHz. If sync MCU interface, PLL should be disabled and use direct 
clock input to CLKI2. 


PLL_VCTRL 15pF 


CLKI 

10kohm 

2-4MHz 
10Mohm 

250pF 

6.4nF 

CLKO 

15pF 


If oscillator input directly to CLKI, this circuit can be omitted 

RC circuit for PLL_VCTRL 

Figure 7-1 : Circuit for PLL enable 

7.2 Embedded Memory 
The 256kByte embedded memory can be access by the modules for different functions. For example, frame 
buffer, SD read/write buffer, internal buffer for JPEG encoding/decoding, encoded JPEG image output and so 
on. 

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7.3 MCU Interface 
Responds to bus request for various kinds of MCU and translates to internal interface signals. SSD1928 can 
support direct and indirect addressing mode. 

7.3.1 Generic #1 addressing Mode 
M/R# 
WE0#, WE1# 
CS# 
D[15:0] 
RD0#, 
RD1# 
Write cycle 
Write Data 0 Write Data 1 Write Data n 
Read cycle 
Address 1 Address n 
Read Data 0 Read Data 1 Read Data n 
Address 0 Address 1 Address n Address 0 A[18:1] 
Note : 

* 13 MCLK is needed for each cycle if WAIT# is not used for interface. 
Figure 7-2 : Generic #1 Interface Timing 

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7.3.2 Generic #2 addressing Mode 
M/R#, 
BHE# 
WE# 
CS# 
D[15:0] 
RD# 
Write cycle 
Write Data 0 Write Data 1 Write Data n 
Read cycle 
Address 1 Address n 
Read Data 0 Read Data 1 Read Data n 
Address 0 Address 1 Address n Address 0 A[18:0] 
Note : 

* 13 MCLK is needed for each cycle if WAIT# is not used for interface. 
Figure 7-3 : Generic #2 Interface Timing 

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7.3.3 8080 Indirect addressing Mode 
8080 Indirect addressing mode consists of 16 or 8 bi-directional data pins (DB15:0), CS#, RD#, WR# 
and D/C#. CS# is the chip select; RD# is the read strobe; WR# is the write strobe; and D/C# is the 
data/command select. They can be used for either 8 bit (DB7:0) or 16 bit (DB15:0) bus protocol. 
CS# failing edge input serves as data read latch signal when RD# is low. D/C# controls whether 
reading the data or reading the command (i.e. status). CS# failing edge input serves as data write 
latch signal when WR# is low. D/C# controls whether writing the data or writing the command (i.e. 
address). In read operation, dummy invalid data read is required after start address. 
The start address counter should be assigned before the data is written or read. The most significant 
bit of the start address is used to select the memory or register (M/R#). During the byte mode access, 
the address counter is automatically incremented by 1 byte after writing or reading the data. During 
the word mode access, the address counter is automatically incremented by 1 word after writing or 
reading the data. The address counter of memory will be returned to 0x00000 if counter = 0x3FFFF 
in byte mode or 0x3FFFE in word mode. 
For 16 bit bus protocol, it can interface with byte or word mode access. The last byte of start address 
in 16-bit access will be used to select byte or word mode (MODE_SL). MODE_SL = 0x00 means byte 
access and MODE_SL = 0x01 means word access. 
Read Burst Termination must be asserted for all JPEG related memory access. If the burst length is 
as small as 1, the read data stage may be reduced to a single dummy read. 
Refer to section 12 for Pseudo-code examples. 

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CS# 

RD#

WR#

D/C# 

DB15:0 
Setup start address 

write M/R# 
AB18:8 
(note 1) 
write AB7:0 
Mode_SL 
(note 2) 
write 
DATA[N] 
write 
DATA[N+1] 
write 
DATA[N+n] 
write 
DATA[N+2] 
Write data 

Note : 

1 
: 
Bit15 represent the M/R#, Bit15 = 1 means memory access, Bit15 = 0 means register access.
Bit14:11 = 0.
Bit10:0 represent the the address AB18:8.
2 
: 
Bit15:8 represent the address AB7:0 and Bit7:0 represent Mode_SL.
Mode_SL to select byte or word access during 16 bit mode. 0x00 means Byte access, 0x01 means word access. 
7 MCLK is needed for each cycle if WAIT# is not used for interface. *
Figure 7-4 : 8080 16 bit Interface Timing (write cycle) 

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Figure 7-5 : 8080 16 bit Interface Timing (read cycle) 

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writeM/R# 
AB18:8(note 1) 
Write AB7:0 
Mode_SL(note 2) 
readDATA[N+1] 
readDATA[N+n-1] 
INVALID(note 3) 
readDATA[N] 
readDATA[N+n] 
Setup start address 
Read data 
write0x00 
write 
0x00 
write 
0x00Read Burst Termination
CS# 

RD#

WR#

D/C# 

DB15:0 

(note 4) 

Note : 

1 
: 
Bit15 represent the M/R#, Bit15 = 1 means memory access, Bit15 = 0 means register access.
Bit14:11 = 0.
Bit10:0 represent the the address AB18:8.
2 
: 
Bit15:8 represent the address AB7:0 and Bit7:0 represent Mode_SL. 
Mode_SL to select byte or word access during 16 bit mode. 0x00 means Byte access, 0x01 means word access. 
3 
: 
Invalid dummy data cycle is needed after adress is written.
4 
: 
Read Burst Termiation must be asserted for all JPEG related memory access.
7 MCLK is needed for each cycle if WAIT# is not used for interface. * 

CS# 

RD#

WR#