ssd1928_1.0.txt

SSD1928英文数据手册

IOVDD 
DB10 
DB9 
DB8 
DB7 
DB6 
DB5 
DB4 
DB3 
COREVDD 
COREVSS 
DB2 
DB1 
DB0 
PLL_DIS 


1 96 

2 95 

3 94 

4 93 

5 92 

6 91 

7 90 

8 89 
9 88 
10 87 
11 86 
12 85 
13 84 
14 83 
15 82 
16 81 
17 80 

SSD1928 

18 79 
19 78 
20 77 
21 76 
22 75 
23 74 
24 73 
25 72 
26 71 
27 70 
28 69 
29 68 
30 67 
31 66 
32 65 

PLL_VCTRLPVDDPVSSCLKICLKOCOREVSSCLKI2DV_CLKIDV_CLKORESET#
AD_RDYAB0AB1AB2AB3

IOVDD

33343536373839404142434445464748

IOVSS

49

AB4

50

AB5

51

128127126125124123122121120119118117116115114113

DV_Y3DV_FIELDDV_HVALIDDV_VVALIDDV_Y4DV_Y5DV_Y6DV_Y7LCD_LINELCD_FRAMELCD_DENLCD_DATA0;D0LCD_DATA1;D1LCD_DATA2;D2IOVDD

IOVSS

112

COREVDD

111

COREVSS

110

LCD_DATA3;D3

AB6AB7AB8COREVSSCOREVDDAB9AB10AB11AB12AB13AB14AB15AB16 

521095310854107551065610557104581035910260101611006299639864 97 

LCD_DATA4;D4LCD_DATA5;D5LCD_DATA6;D6;SCKLCD_DATA7;D7;SDALCD_SHIFTIOVDDIOVSSCOREVSSCOREVDDLCD_D/C#
LCD_CS#
LCD_WR#;LCD_RD/WR#
LCD_RD#;LCD_E 

GPIO4 
GPIO3 
GPIO2 
GPIO1 
GPIO0 
IOVSS 
IOVDD 
COREVDD 
COREVSS 
DV_ENB 
DV_RESET 
I2C_SCL 
I2C_SDA 
CNF6 
CNF4 
CNF3 
CNF2 
CNF1 
CNF0 
AD_MODE 
SD_WP 
SD_CLK 
SD_CMD 
COREVDD 
COREVSS 
SD_CD 
SD_DATA3 
SD_DATA2 
SD_DATA1 
SD_DATA0 
AB18 
AB17 

Solomon Systech Mar 2007 P 10/46 Rev 1.0 SSD1928 

Table 5-1 : LQFP Pin Assignment Table 

Pin # Signal Name Pin # Signal Name Pin # Signal Name Pin # Signal Name 
1 DV_Y2 33 PLL_VCTRL 65 AB17 97 LCD_RD#;LCD_E 
2 DV_Y1 34 PVDD 66 AB18 98 LCD_WR#;LCD_ 
RD/WR# 
3 DV_Y0 35 PVSS 67 SD_DATA0 99 LCD_CS# 
4 M/R# 36 CLKI 68 SD_DATA1 100 LCD_D/C# 
5 COREVDD 37 CLKO 69 SD_DATA2 101 COREVDD 
6 COREVSS 38 COREVSS 70 SD_DATA3 102 COREVSS 
7 WE1# 39 CLKI2 71 SD_CD 103 IOVSS 
8 WE0# 40 DV_CLKI 72 COREVSS 104 IOVDD 
9 RD/WR# 41 DV_CLKO 73 COREVDD 105 LCD_SHIFT 
10 RD# 42 RESET# 74 SD_CMD 106 LCD_DATA7;D7; 
SDA 
11 CS# 43 TESTO 75 SD_CLK 107 LCD_DATA6;D6; 
SCK 
12 DB15 44 AB0 76 SD_WP 108 LCD_DATA5;D5 
13 DB14 45 AB1 77 AD_MODE 109 LCD_DATA4;D4 
14 DB13 46 AB2 78 CNF0 110 LCD_DATA3;D3 
15 DB12 47 AB3 79 CNF1 111 COREVSS 
16 DB11 48 IOVDD 80 CNF2 112 COREVDD 
17 IOVSS 49 IOVSS 81 CNF3 113 IOVSS 
18 IOVDD 50 AB4 82 CNF4 114 IOVDD 
19 DB10 51 AB5 83 CNF6 115 LCD_DATA2;D2 
20 DB9 52 AB6 84 I2C_SDA 116 LCD_DATA1;D1 
21 DB8 53 AB7 85 I2C_SCL 117 LCD_DATA0;D0 
22 DB7 54 AB8 86 DV_RESET 118 LCD_DEN 
23 DB6 55 COREVSS 87 DV_ENB 119 LCD_FRAME 
24 DB5 56 COREVDD 88 COREVSS 120 LCD_LINE 
25 DB4 57 AB9 89 COREVDD 121 DV_Y7 
26 DB3 58 AB10 90 IOVDD 122 DV_Y6 
27 COREVDD 59 AB11 91 IOVSS 123 DV_Y5 
28 COREVSS 60 AB12 92 GPIO0 124 DV_Y4 
29 DB2 61 AB13 93 GPIO1 125 DV_VVALID 
30 DB1 62 AB14 94 GPIO2 126 DV_HVALID 
31 DB0 63 AB15 95 GPIO3 127 DV_FIELD 
32 PLL_DIS 64 AB16 96 GPIO4 128 DV_Y3 

SSD1928 Rev 1.0 P 11/46 Mar 2007 Solomon Systech 

6 PIN DESCRIPTIONS 

Key: 

I = Input 
O =Output 
IO = Bi-directional (input / output) 
P = Power pin 
AN = Analog 
LIS = LVCMOS Schmitt input 
LB2 = LVCMOS IO buffer (8mA/-8mA at 3.3V) 
LB3 = LVCMOS IO buffer (16mA/-16mA at 3.3V) 
LO1 = LVCMOS output buffer (2mA/-2mA at 3.3V) 
LO2 = LVCMOS output buffer (4mA/-4mA at 3.3V) 
LO3 = LVCMOS output buffer (16mA/-16mA at 3.3V) 
LT2 = Tri-state output buffer (8mA/-8mA at 3.3V) 
Hi-Z = High impedance 


6.1 Global Signal 
Table 6-1 : Host Interface Pin Descriptions 

Pin Name Type LQFP Pin # Cell RESET# 
State Description 
CLKI2 I 39 LIS -
This pin can used as clock source input when PLL is 
disable. When synchronized MCU interface is 
selected, connect the bus clock to CLKI2 and 
disable the PLL by connecting the PLL_DIS pin to 
IOVDD. If the PLL is enabled. CLKI2 has to be pull-
up or pull-down. 
CLKI, CLKO IO 36, 37 AN -
These two pins are the source clock of internal PLL. 
It accepts clock frequency from 2MHz to 4MHz. 
The clock source can be either oscillator or crystal. 
If 4-pin oscillator or a slow clock source is 
available, please connect the output of oscillator or 
the clock source to CLKI and leave the CLKO pin 
floating. 
PLL_DIS I 32 LIS -
PLL disable control pin. 
PLL_DIS = IOVDD, PLL disabled (When PLL is 
disable, the master clock is directly fed from CLKI2 
pin) 
PLL_DIS = IOVSS, PLL enabled 
PLL_VCTRL I 33 AN -
Control for PLL. 
If internal PLL is selected, RC circuit should be 
connected. Refer to 7.1. 
Leave this pin floating if PLL is disabled. 
RESET# I 42 LIS -
Master chip reset. 
Active low input to set all internal registers to the 
default state and to force all signals to their inactive 
states. It is recommended to place a 0.1μF capacitor 
to VSS. 
Note 
(1) When reset state is released (RESET# = “H”), 
normal operation can be started after 3 MCLK 
period. 

Solomon Systech Mar 2007 P 12/46 Rev 1.0 SSD1928 


6.2 MCU Interface 
Table 6-2 : MCU Interface Pin Descriptions 

Pin Name Type LQFP Pin # Cell RESET# 
State Description 
AB0 I 44 LIS 0 
This input pin has multiple functions. 
. For Generic #1, this pin is not used and should 
be connected to VSS. 
. For Generic #2, this is an input of system 
address bit 0 (A0). 
. For 8080, this pin is not used and should be 
connected to VSS. 
AB[18:4, 2, 
1] I 45-46, 50-54, 
57-66 LIS 0 
System address bus bits 18-4, 2, 1 for direct address 
mode. 
For 8080, those pins are not used and should be 
connected to VSS. 
AB[3] I 47 LIS 0 
This input pin has multiple functions. 
. System address bus bit 3 for direct address 
mode 
. For 8080, this pin is used as data / command 
select, D/C#. 
DB[15:0] IO 12-16, 19-26, 
29-31 LB2 Hi-Z Bi-directional system data bus 15:0. 
WE0# I 8 LIS 1 
This input pin has multiple functions. 
. For Generic #1, this is an input of the write 
enable signal for the lower data byte (WE0#). 
. For Generic #2, this is an input of the write 
enable signal (WE#). 
. For 8080, this is an input of write enable signal, 
WR# 
WE1# I 7 LIS 1 
This input pin has multiple functions. 
. For Generic #1, this is an input of the write 
enable signal for the upper data byte (WE1#). 
. For Generic #2, this is an input of the byte 
enable signal for the high data byte (BHE#). 
. For 8080, this pin is not used and should be 
connected to VSS. 
CS# I 11 LIS 1 Chip select input. 
M/R# I 4 LIS 0 
. For 8080, this pin is not used and should be 
connected to VSS. 
. For other interfaces, this input pin is used to 
select the display buffer or internal registers of 
the SSD1928. M/R# is set high to access the 
display buffer and low to access the registers. 
RD/WR# I 9 LIS 1 
This input pin has multiple functions. 
. For Generic #1, this is an input of the read 
signal for the upper data byte (RD1#). 
. For Generic #2, this pin must be tied to IOVDD . 
. For 8080, this pin is not used and should be 
connected to VSS. 

SSD1928 Rev 1.0 P 13/46 Mar 2007 Solomon Systech 

Pin Name Type LQFP Pin # Cell RESET# 
State Description 
RD# I 10 LIS 1 
This input pin has multiple functions. 
. For Generic #1, this is an input of the read 
signal for the lower data byte (RD0#). 
. For Generic #2, this is an input of the read 
command (RD#). 
. For 8080, this is an input of read enable signal, 
RD# 

See Table 6-10 : Host Bus Interface Pin Mapping for summary. 

6.3 Display Interface 
Table 6-3 : Display Interface Pin Descriptions 

Pin Name Type LQFP Pin 
# Cell RESET# 
State Description 
LCD_DATA[5:0];D[5 
:0] O 108-110, 
115-117 LO3 0 
If RGB dump panel is selected, those pins are RGB 
dump data bits 5-0. 
If MCU smart parallel panel is selected, those pins are 
data bits 5-0 
If MCU smart serial panel is selected, those signals 
are not in used. 
LCD_DATA6;D6;SC 
K O 107 LO3 0 
If RGB dump panel is selected, this pin is RGB dump 
data bit 6. 
If MCU smart parallel panel is selected, this pin is 
data bit 6 
If MCU smart serial panel is selected, this pin 
becomes serial clock signal, SCK. 
LCD_DATA7;D7;SD 
A O 106 LO3 0 
If RGB dump panel is selected, this pin is RGB dump 
data bit 7. 
If MCU smart parallel panel is selected, this pin is 
data bit 7 
If MCU smart serial panel is selected, this pin 
becomes serial data signal, SDA. 
LCD_FRAME O 119 LO3 0 Frame Pulse (vertical sync) 
LCD_LINE O 120 LO3 0 Line Pulse (horizontal sync) 
LCD_SHIFT O 105 LO3 0 Shift Clock 
LCD_DEN O 118 LO3 0 
This output pin has multiple functions. 
. Display enable (LDEN) for TFT panels 
. LCD backplane bias signal (MOD) for all other 
LCD panels 
LCD_ D/C# O 100 LO3 0 
If RGB dump panel is selected, this signal is not in 
used. 
If MCU smart parallel and serial panel is selected, this 
signal is data/command select, D/C#. 
LCD_ CS# O 99 LO3 0 
If RGB dump panel is selected, this signal is not in 
used. 
If MCU smart parallel and serial panel is selected, this 
signal is chip select, CS#. 
LCD_WR#;LCD_R/ 
W# O 98 LO3 0 
If RGB dump panel is selected, this signal is not in 
used 
If MCU smart parallel 8080 panel is selected, this 
signal is WR#. 
If MCU smart parallel 6800 panel is selected, this 
signal is R/W#. 
If MCU smart serial panel is selected, this signal is 

Solomon Systech Mar 2007 P 14/46 Rev 1.0 SSD1928 

not in used. 
LCD_RD#;LCD_E O 97 LO3 0 
If RGB dump panel is selected, this signal is not in 
used. 
If MCU smart parallel 8080 panel is selected, this 
signal is RD#. 
If MCU smart parallel 6800 panel is selected, this 
signal is E. 
If MCU smart serial panel is selected, this signal is 
not in used. 

See Table 6-11 : LCD Interface Pin Mapping for summary. 

6.4 
CMOS Camera Interface 
Table 6-4 : CMOS Camera Interface Pin Descriptions 
Pin Name Type LQFP 
Pin # Cell RESET# 
State Description 
DV_CLKI I 40 LIS -Video clock input from video module 
DV_CLKO O 41 LO3 0 Video clock output to video module 
DV_Y[7:0] I 121-124, 
128, 1-3 LIS -8 bits Luminance/Chrominance data input 
DV_FIELD I 127 LIS -Odd / Even field input 
DV_HVALID I 126 LIS -Horizontal valid, sometimes will be used as Horizontal 
SYNC input 
DV_VVALID I 125 LIS -Vertical valid, sometimes will be used as Vertical 
SYNC input 
DV_ENB O 87 LO2 0 Video module enable 
DV_RESET O 86 LO1 0 Video module reset 
I2C_SDA IO 84 LB2 -I2C serial data. A pull-up resistor should be used to 
resolve any data contention issues. 
I2C_SCL IO 85 LB2 -I2C serial clock. A pull-up resistor should be used to 
resolve any data contention issues. 

6.5 MMC/SD/SDIO Interface 
Table 6-5 : MMC/SD/SDIO Interface Pin Descriptions