ssd1928_1.0.txt

SSD1928英文数据手册

SOLOMON SYSTECH 
SEMICONDUCTOR TECHNICAL DATA 

SSD1928 


Advance Information 

JPEG Codec 
Camera and video input port 
SD interface 
256K Embedded Display SRAM 
Image Processor 
CMOS 


This document contains information on a new product. Specifications and information herein are subject to change 
without notice. 

http://www.solomon-systech.com 

Mar 2007 SSD1928 Rev 1.0 P 1/46 

Copyright . 2007 Solomon Systech Limited 



CONTENTS 

1 GENERAL DESCRIPTION ....................................................................................................... 6 


2 FEATURES.................................................................................................................................. 6 


2.1 CAMERA INPUT PORT ............................................................................................................................................6 
2.2 HARDWARE JPEG CODEC ....................................................................................................................................6 
2.3 2D GRAPHIC ENGINE ............................................................................................................................................7 
2.4 LCD GRAPHIC CONTROLLER................................................................................................................................7 
2.5 LCD PANEL INTERFACE .......................................................................................................................................7 
2.6 HOST MCU INTERFACE ........................................................................................................................................8 
2.7 MMC/SD INTERFACE...........................................................................................................................................8 
2.8 I/O INTERFACE .....................................................................................................................................................8 
2.9 MISCELLANEOUS ..................................................................................................................................................8 
2.10 PACKAGE..............................................................................................................................................................8 
3 ORDERING INFORMATION ................................................................................................... 8 


4 BLOCK DIAGRAM .................................................................................................................... 9 


5 PIN ARRANGEMENT.............................................................................................................. 10 


5.1 128 PIN LQFP.....................................................................................................................................................10 
6 PIN DESCRIPTIONS................................................................................................................ 12 


6.1 GLOBAL SIGNAL.................................................................................................................................................12 
6.2 MCU INTERFACE................................................................................................................................................13 
6.3 DISPLAY INTERFACE...........................................................................................................................................14 
6.4 CMOS CAMERA INTERFACE...............................................................................................................................15 
6.5 MMC/SD/SDIO INTERFACE ...............................................................................................................................15 
6.6 CONFIGURATION.................................................................................................................................................16 
6.7 MISCELLANEOUS ................................................................................................................................................16 
6.8 POWER AND GROUND .........................................................................................................................................16 
6.9 SUMMARY OF CONFIGURATION ...........................................................................................................................17 
6.10 HOST BUS INTERFACE PIN MAPPING ...................................................................................................................18 
6.11 LCD INTERFACE PIN MAPPING...........................................................................................................................18 
6.12 DATA BUS ORGANIZATION.................................................................................................................................18 
7 FUNCTIONAL BLOCK DESCRIPTIONS............................................................................. 20 


7.1 PHASE LOCK LOOP (PLL)...................................................................................................................................20 
7.2 EMBEDDED MEMORY .........................................................................................................................................20 
7.3 MCU INTERFACE................................................................................................................................................21 
7.3.1 Generic #1 addressing Mode ......................................................................................................................21 
7.3.2 Generic #2 addressing Mode ......................................................................................................................22 
7.3.3 8080 Indirect addressing Mode ..................................................................................................................23 
7.4 REGISTERS..........................................................................................................................................................28 
7.5 JPEG ENCODER/DECODER .................................................................................................................................28 
7.6 IMAGE CAPTURE INTERFACE ...............................................................................................................................28 
7.7 2D ENGINE .........................................................................................................................................................28 
7.8 DISPLAY INTERFACE...........................................................................................................................................28 
7.9 MMC/SD/SDIO INTERFACE ...............................................................................................................................28 
7.10 GENERAL PURPOSE INPUT/OUTPUT (GPIO) ........................................................................................................28 
8 MAXIMUM RATINGS ............................................................................................................. 29 


9 DC CHARACTERISTICS ........................................................................................................ 30 


10 AC CHARACTERISTICS..................................................................................................... 31 


Solomon Systech Mar 2007 P 2/46 Rev 1.0 SSD1928 

10.1 CLOCK TIMING ...................................................................................................................................................31 
10.1.1 Input Clocks ...............................................................................................................................................31 
10.2 CPU INTERFACE TIMING ....................................................................................................................................32 
10.2.1 Generic #1 Interface Timing.......................................................................................................................32 
10.2.2 Generic #2 Interface Timing (e.g. ISA).......................................................................................................34 
10.2.3 8080 Indirect Interface Timing ...................................................................................................................36 
11 APPLICATION EXAMPLES ............................................................................................... 37 


11.1 APPLICATION DIAGRAM .....................................................................................................................................37 
12 PSEUDO-CODE EXAMPLES FOR INDIRECT ADDRESS MODE............................... 40 


12.1 8080 INDIRECT ADDRESS MODE ...........................................................................................................................40 
13 PACKAGE INFORMATION................................................................................................ 45 


13.1 PACKAGE MECHANICAL DRAWING FOR 128 PINS LQFP......................................................................................45 
SSD1928 Rev 1.0 P 3/46 Mar 2007 Solomon Systech 

TABLES 

TABLE 3-1 : ORDERING INFORMATION .................................................................................................................................8 
TABLE 5-1 : LQFP PIN ASSIGNMENT TABLE .......................................................................................................................11 
TABLE 6-1 : HOST INTERFACE PIN DESCRIPTIONS ...............................................................................................................12 
TABLE 6-2 : MCU INTERFACE PIN DESCRIPTIONS ...............................................................................................................13 
TABLE 6-3 : DISPLAY INTERFACE PIN DESCRIPTIONS ..........................................................................................................14 
TABLE 6-4 : CMOS CAMERA INTERFACE PIN DESCRIPTIONS..............................................................................................15 
TABLE 6-5 : MMC/SD/SDIO INTERFACE PIN DESCRIPTIONS..............................................................................................15 
TABLE 6-6 : CONFIGURATION PIN DESCRIPTIONS ................................................................................................................16 
TABLE 6-7 : MISCELLANEOUS PIN DESCRIPTIONS ...............................................................................................................16 
TABLE 6-8 : POWER AND GROUND PIN DESCRIPTIONS ........................................................................................................16 
TABLE 6-9 : SUMMARY OF CONFIGURATION PINS................................................................................................................17 
TABLE 6-10 : HOST BUS INTERFACE PIN MAPPING..............................................................................................................18 
TABLE 6-11 : LCD INTERFACE PIN MAPPING ......................................................................................................................18 
TABLE 6-12 : DATA BUS ORGANIZATION ............................................................................................................................18 
TABLE 6-13 : PIN STATE SUMMARY ...................................................................................................................................19 
TABLE 8-1: ABSOLUTE MAXIMUM RATINGS .......................................................................................................................29 
TABLE 8-2 : RECOMMENDED OPERATING CONDITIONS .......................................................................................................29 
TABLE 9-1 : ELECTRICAL CHARACTERISTICS FOR IOVDD = 3.3V TYPICAL ..........................................................................30 
TABLE 10-1 : CLOCK INPUT REQUIREMENTS FOR CLKI ......................................................................................................31 
TABLE 10-2 : OSCILLATOR CLOCK INPUT REQUIREMENTS FOR CLKI2...............................................................................31 
TABLE 10-3 : GENERIC #1 INTERFACE TIMING ....................................................................................................................33 
TABLE 10-4 : GENERIC #2 INTERFACE TIMING ....................................................................................................................35 
TABLE 10-5 : 8080 INTERFACE TIMING ...............................................................................................................................36 


Solomon Systech Mar 2007 P 4/46 Rev 1.0 SSD1928 

FIGURES 

FIGURE 4-1 : SSD1928 BLOCK DIAGRAM.............................................................................................................................9 
FIGURE 5-1 : PINOUT DIAGRAM – 128 PIN LQFP (TOPVIEW)...............................................................................................10 
FIGURE 7-1 : CIRCUIT FOR PLL ENABLE ..............................................................................................................................20 
FIGURE 7-2 : GENERIC #1 INTERFACE TIMING .....................................................................................................................21 
FIGURE 7-3 : GENERIC #2 INTERFACE TIMING .....................................................................................................................22 
FIGURE 7-4 : 8080 16 BIT INTERFACE TIMING (WRITE CYCLE).............................................................................................24 
FIGURE 7-5 : 8080 16 BIT INTERFACE TIMING (READ CYCLE) ..............................................................................................25 
FIGURE 7-6 : 8080 8 BIT INTERFACE TIMING (WRITE CYCLE)...............................................................................................26 
FIGURE 7-7 : 8080 8 BIT INTERFACE TIMING (READ CYCLE) ................................................................................................27 
FIGURE 10-1 : GENERIC #1 INTERFACE TIMING ...................................................................................................................32 
FIGURE 10-2 : GENERIC #2 INTERFACE TIMING ...................................................................................................................34 
FIGURE 10-3 : 8080 INTERFACE TIMING ..............................................................................................................................36 
FIGURE 11-1 : TYPICAL SYSTEM DIAGRAM (GENERIC #1 BUS) ...........................................................................................37 
FIGURE 11-2 : TYPICAL SYSTEM DIAGRAM (GENERIC #2 BUS) ...........................................................................................38 
FIGURE 11-3:TYPICAL SYSTEM DIAGRAM (INDIRECT 808016 BIT BUS)............................................................................39 


SSD1928 Rev 1.0 P 5/46 Mar 2007 Solomon Systech 

1 GENERAL DESCRIPTION 

SSD1928 is an image processor designed for advanced car AV device with image capture and process 
features. 

It offers camera or DVD input port, image processing unit and hardware JPEG codec to encode the 
captured image into JPEG file. The files can be saved into SD/MMC card through SD interface. The 
JPEG file is retrieved back from SD/MMC card, decoded and displayed on LCD panel through LCD 
interface. This interface supports various kinds of LCD panel like STN, CSTN and TFT. 

The LCD controller of SSD1928 supports LCD panel for mobile phone with size, for example, 176x220 
and 240x160 resolution at color depth 1, 2, 4, 8, 16 and 32 bit-per-pixel (bpp). For 16 and 32 bpp, 
SSD1928 provides 2D graphics acceleration features like virtual display, image rotation, cursor display, 
line drawing, BitBLT with raster operation, color fill, color expansion etc. 

SSD1928 is able to interface different type of generic microcontrollers that are popular in handheld 
devices market. It also support indirect addressing mode which can minimize the pin count of control 
signals. 

Internal PLLs is built such that only single clock is required for SSD1928 to generate clocks for blocks 
with various clock speed requirement. 

With advanced power management design, SSD1928 is suitable for low power consumption and 
advanced image applications like car AV product etc. The SSD1928 is available in LQFP package. 

2 FEATURES 

The main features of the SSD1928 are as follows: 

2.1 Camera input port 
. 
Digital signal input and format 
a. 
Support 8-bit YUV422 CCIR601, CCIR656 
b. 
Support progressive video signal only 
c. 
Capture still image size up to 2.0M pixel resolution 
d. 
Max input frame frequency: 30fps at 2.0M pixel resolution 
. 
Scaling 
a. 
Support fix size low quality decimation (1, 2, 4, 8, 16) 
. 
Image Preview 
a. 
Support cropping and decimation for preview up to QVGA (320x240) size 
. 
Color conversion 
a. 
For JPEG encoding, only YUV input source is supported 
b. 
Fix YUV -> RGB color conversion implementation from YUV422 -> RGB565 and YUV422 
-> RGB888 format (32-bit, including 8-bit alpha blending value) 
c. 
Y, U and V components can be adjusted to set brightness and contrast. 
2.2 Hardware JPEG Codec 
. 
Hardware codec to encode and decode JPEG image with variable size up to 1280 x 1024. 
. 
JPEG codec is consisted of the following hardware module 
a. Discrete Cosine Transform (DCT) and Inverse Discrete Cosine Transform (iDCT) 
Solomon Systech Mar 2007 P 6/46 Rev 1.0 SSD1928 

b. 
Quantization calculation with table downloadable by software 
c. 
Zigzag and run-length coding 
d. 
Huffman encoding and decoding with table downloadable by software 
. 
For viewing JPEG image on LCD panel, the JPEG decoder can decimate and crop the image such that 
the length is in multiple of 8. 
2.3 2D Graphic Engine 
. 
Screen panning and scrolling – virtual display mode 
. 
Image rotation including 0, 90, 180, 270 degree 
. 
Two cursors with three colors and transparency selection. Cursor blinking is available 
. 
Line drawing 
. 
Rectangle drawing 
. 
Ellipse drawing 
. 
Bit block transfer (BitBLT) 
a. 
Host to frame buffer 
b. 
Frame buffer to frame buffer 
c. 
Total 256 three-operand raster operations (ROP3) working with BitBLT 
d. 
Pattern BitBLT: Source image is repeatedly filled up destination block 
e. 
Stretch BitBLT: Stretch the source image to a destination larger or smaller than the source 
f. 
Color Expansion: Monochrome color is expanded to either background or foreground color. 
g. 
Color Conversion: Source color is converted between RGB and YUV to destination block -> 
YUV overlay RGB background / RGB overlay YVU background. 
h. 
Color Fill: Fill a rectangular block with a single color. 
2.4 LCD Graphic Controller 
. 
Support 1, 2, 4, 8, 16 and 32 bit-per-pixel (bpp) color depth 
. 
In 32bpp mode, each pixel is consisted of 8-bit red, 8-bit green, 8-bit blue and 8-bit alpha channel for 
controlling the transparency of the image. 
. 
In 1, 2, 4, 8bpp mode, it can display still image and has no 2D graphic engine feature available. 
. 
Arbitrary image size supported up to horizontal resolution of 512 
2.5 LCD Panel Interface 
. 
Support the following type of LCD panels: 
a. 
Monochrome and color STN 4/8 bit LCD interface 
b. 
8 bit Serial TFT interface 
c. 
8 bit Delta panel with sub-pixel accuracy algorithm 
d. 
Smart LCD through SPI and 8-bit MCU (8080, 6800) interface 
. 
For STN and CSTN panel, spatial and dynamic dithering is available to increase color depth. 
a. 
16 gray shades for each color component when applying frame rate control only 
b. 
64 gray shades for each color component when applying frame rate control and dithering 
. 
LCD panel power on and off sequencing 
SSD1928 Rev 1.0 P 7/46 Mar 2007 Solomon Systech 

2.6 Host MCU interface 
. 
Support the following MCU interface 
a. 
SRAM interface (e.g. generic ARM core type MCU) 
b. 
ISA interface for MCU like NEC MIPS 
c. 
8/16 bits 8080 indirect addressing mode 
. 
Support synchronous and asynchronous interface communication 
. 
Memory mapped I/O 
. 
Big/Little endian support 
2.7 MMC/SD Interface 
. 
Compatible with “The MultiMedia Card System Specification version 3.0” 
. 
Compatible with “SD Memory Card Specification version 1.0” and “SDIO Card Specification version 
1.0” 
. 
Block transfer from/to external host 
. 
Block transfer from/to internal memory 
. 
Supports many SD functions including multiple I/O and combined I/O and memory 
2.8 I/O Interface 
. 
I2C master to control CMOS sensor 
. 
5 GPIOs 
2.9 Miscellaneous 
. 
Embedded 256K bytes SRAM 
. 
Single clock input 
. 
Integrated PLL 
. 
1.8V core voltage with built in regulator for single voltage input 
. 
Advanced power management to cut off the power for modules that are idle. 
2.10 Package 
. 
128-pin LQFP package 
3 ORDERING INFORMATION 
Table 3-1 : Ordering Information 

Ordering Part Number Package Form 
SSD1928QL9 128 LQFP 

Solomon Systech Mar 2007 P 8/46 Rev 1.0 SSD1928 

BLOCK DIAGRAM 

Figure 4-1 : SSD1928 Block Diagram 

Image Capture 
interface 
MMC/ 
SD Interface 
Hardware 
JPEG Codec 
Embedded SRAM 
256K Bytes 
Memory 
Controller 
LCD 
Interface 
Register 
2D Graphic 
Engine 
MCU 
Interface 
PLLs 
MMC/ SD 
Card/ SDIO 
Host MCU 
LCD panel 
I2C 
Master 
Power 
Management 
GPIO 
Image 
source 

External 
clock 

SSD1928 Rev 1.0 P 9/46 Mar 2007 Solomon Systech 

5 PIN ARRANGEMENT 

5.1 128 pin LQFP 
Figure 5-1 : Pinout Diagram – 128 pin LQFP (Topview) 

DV_Y2 
DV_Y1 
DV_Y0 
M/R# 
COREVDD 
COREVSS 
WE1# 
WE0# 
RD/WR# 
RD# 
CS# 
DB15 
DB14 
DB13 
DB12 
DB11 
IOVSS