at91sam7s.h

μITRON4.0 source code for ARM

#define TOFF_PWM_IER    0x0010			/* PWM Interrupt Enable Register (W) */
#define TOFF_PWM_IDR    0x0014			/* PWM Interrupt Disable Register (W) */
#define TOFF_PWM_IMR    0x0018			/* PWM Interrupt Mask Register (R) */
#define TOFF_PWM_ISR    0x001C			/* PWM Interrupt Status Register (R) */
#define TADR_PWMC_BASE  0xFFFCC200		/* PWM Channel0 BASE address */
#define CN_WINDOW       0x0020			/* PWM Channel Window size */
#define TADR_PWMC0_BASE (TADR_PWMC_BASE)
#define TADR_PWMC1_BASE (TADR_PWMC_BASE+CN_WINDOW)
#define TOFF_PWM_CMR    0x0000			/* PWM Channel Mode Register (R/W) */
#define TOFF_PWM_CDTY   0x0004			/* PWM Channel Duty Cycle Register (R/W) */
#define TOFF_PWM_CPRD   0x0008			/* PWM Channel Period Register (R/W) */
#define TOFF_PWM_CCNT   0x000C			/* PWM Channel Counter Register (R) */
#define TOFF_PWM_CUPD   0x0010			/* PWM Channel Update Register (W) */


/*
 *  SYNCHRONOUS SERIAL CONTROLLER (SSC)
 */
#define TADR_SSC_BASE    0xFFFD4000		/* Synchronous Serial Controller BASE Address */
#define TOFF_SSC_CR      0x0000			/* Control Register (W) */
#define TOFF_SSC_CMR     0x0004			/* Clock Mode Register (R/W) */
#define TOFF_SSC_RCMR    0x0010			/* Receive Clock Mode Register (R/W) */
#define TOFF_SSC_RFMR    0x0014			/* Receive Frame Mode Register (R/W) */
#define TOFF_SSC_TCMR    0x0018			/* Transmit Clock Mode Register (R/W) */
#define TOFF_SSC_TFMR    0x001C			/* Transmit Frame Mode Register (R/W) */
#define TOFF_SSC_RHR     0x0020			/* Receive Holding Register (R) */
#define TOFF_SSC_THR     0x0024			/* Transmit Holding Register (R) */
#define TOFF_SSC_RSHR    0x0030			/* Receive Sync. Holding Register (R) */
#define TOFF_SSC_TSHR    0x0034			/* Transmit Sync. Holding Register (R/W) */
#define TOFF_SSC_RC0R    0x0038			/* Receive Compare 0 Register (R/W) */
#define TOFF_SSC_RC1R    0x003C			/* Receive Compare 1 Register (R/W) */
#define TOFF_SSC_SR      0x0040			/* Status Register (R) */
#define TOFF_SSC_IER     0x0044			/* Interrupt Enable Register (W) */
#define TOFF_SSC_IDR     0x0048			/* Interrupt Disable Register (W) */
#define TOFF_SSC_IMR     0x004C			/* Interrupt Mask Register (R) */


/*
 *  ANALOG-TO-DIGITAL CONVERTER (ADC)
 */
#define TADR_ADC_BASE    0xFFFD8000		/* Analog-to-digital Converter BASE address */
#define TOFF_ADC_CR      0x0000			/* Control Register (W) */
#define TOFF_ADC_MR      0x0004			/* Mode Register (R/W) */
#define TOFF_ADC_CHER    0x0010			/* Channel Enable Register (W) */
#define TOFF_ADC_CHDR    0x0014			/* Channel Disable Register (W) */
#define TOFF_ADC_CHSR    0x0018			/* Channel Status Register (R) */
#define TOFF_ADC_SR      0x001C			/* Status Register (R) */
#define TOFF_ADC_LCDR    0x0020			/* Last Converted Data Register (R) */
#define TOFF_ADC_IER     0x0024			/* Interrupt Enable Register (W) */
#define TOFF_ADC_IDR     0x0028			/* Interrupt Disable Register (W) */
#define TOFF_ADC_IMR     0x002C			/* Interrupt Mask Register (R) */
#define TOFF_ADC_CDR     0x0030			/* Channel Data Register (R) */
#define TOFF_ADC_CDR0    0x0030			/* Channel Data Register0 (R) */
#define TOFF_ADC_CDR1    0x0034			/* Channel Data Register1 (R) */
#define TOFF_ADC_CDR2    0x0038			/* Channel Data Register2 (R) */
#define TOFF_ADC_CDR3    0x003C			/* Channel Data Register3 (R) */
#define TOFF_ADC_CDR4    0x0040			/* Channel Data Register4 (R) */
#define TOFF_ADC_CDR5    0x0044			/* Channel Data Register5 (R) */
#define TOFF_ADC_CDR6    0x0048			/* Channel Data Register6 (R) */
#define TOFF_ADC_CDR7    0x004C			/* Channel Data Register7 (R) */


/*
 *  SERIAL PERIPHERAL INTERFACE (SPI)
 */
#define TADR_SPI_BASE    0xFFFE0000		/* Serial Peripheral Interfcae BASE Address */
#define TOFF_SPI_CR      0x0000			/* Control Register (W) */
#define TOFF_SPI_MR      0x0004			/* Mode Register (R/W) */
#define TOFF_SPI_RDR     0x0008			/* Receive Data Register (R) */
#define TOFF_SPI_TDR     0x000C			/* Transmit Data Register (W) */
#define TOFF_SPI_SR      0x0010			/* Status Register (R) */
#define TOFF_SPI_IER     0x0014			/* Interrupt Enable Register (W) */
#define TOFF_SPI_IDR     0x0018			/* Interrupt Disable Register (W) */
#define TOFF_SPI_IMR     0x001C			/* Interrupt Mask Register (R) */
#define TOFF_SPI_CSR0    0x0030			/* Chip Select Register0 (R/W) */
#define TOFF_SPI_CSR1    0x0034			/* Chip Select Register1 (R/W) */
#define TOFF_SPI_CSR2    0x0038			/* Chip Select Register2 (R/W) */
#define TOFF_SPI_CSR3    0x003C			/* Chip Select Register3 (R/W) */

/*
 *  PERIPHERAL DMA CONTROLLER (PDC)
 */
#define TOFF_PDC_RPR    0x0100			/* Receive Pointer Register (R/W) */
#define TOFF_PDC_RCR    0x0104			/* Receive Counter Register (R/W) */
#define TOFF_PDC_TPR    0x0108			/* Transmit Pointer Register (R/W) */
#define TOFF_PDC_TCR    0x010C			/* Transmit Counter Register (R/W) */
#define TOFF_PDC_RNPR   0x0110			/* Receive Next Pointer Register (R/W) */
#define TOFF_PDC_RNCR   0x0114			/* Receive Next Counter Register (R/W) */
#define TOFF_PDC_TNPR   0x0118			/* Transmit Next Pointer Register (R/W) */
#define TOFF_PDC_TNCR   0x011C			/* Transmit Next Counter Register (R/W) */
#define TOFF_PDC_PTCR   0x0120			/* PDC Transfar Control Register (W) */
#define TOFF_PDC_PTSR   0x0124			/* PDC Transfar Status Register (R) */


#if defined (__AT91SAM7S128__)
// 128kbytes,512pages of 256bytes
#define FLASH_PAGE_NB           512
#define FLASH_PAGE_LOCK         64
#define FLASH_PAGE_SIZE         256
#define FLASH_PAGE_SIZE_BYTE    256
#define FLASH_PAGE_SIZE_LONG    64
// 8lockbits, protecting 8sectors of 64pages
#define FLASH_LOCK_BITS_SECTOR  8
#define FLASH_SECTOR_PAGE       64
#define FLASH_LOCK_BITS         8

#define SRAM_SIZE               (32U*1024U)

#elif defined (__AT91SAM7S256__)
// 256kbytes,1024pages of 256bytes
#define  FLASH_PAGE_NB          1024
#define  FLASH_PAGE_LOCK        65
#define  FLASH_PAGE_SIZE        256
#define  FLASH_PAGE_SIZE_BYTE   256
#define  FLASH_PAGE_SIZE_LONG   64
// 16lockbits, protecting 16sectors of 64pages
#define  FLASH_LOCK_BITS_SECTOR 16
#define  FLASH_SECTOR_PAGE      64
#define  FLASH_LOCK_BITS        16

#define SRAM_SIZE               (64U*1024U)

#endif
#define FLASH_BASE_ADDRESS      0x00100000
#define SRAM_BASE_ADDRESSS      0x00200000

#define MCK	                    48054857

/*
 * ボ〖レ〖ト
 */
#define BAUDRATE   38400

#if defined (__AT91SAM7A3__)
#define TOFF_PIO_PDR_VAL   ((1<<30U)|(1<<31U))
#else
#define TOFF_PIO_PDR_VAL   ((1<<9U)|(1<<10U))
#endif /* AT91SAM7A3 */

#ifndef TOPPERS_MACRO_ONLY
        
/*
 * IRC拎侯簇眶
 */

/*
 * 充哈み妥滇のマスク
 */
Inline void
at91sam7s_disable_int(uint32_t mask)
{
    sil_wrw_mem((void *)(TADR_AIC_BASE + TOFF_AIC_IDCR), mask);	
}

/*
 * 充哈み妥滇のマスクの豺近
 */
Inline void
at91sam7s_enable_int(uint32_t mask)
{
    sil_wrw_mem((void *)(TADR_AIC_BASE + TOFF_AIC_IECR), mask);	
}

/*
 * 充哈み妥滇のクリア
 */
Inline void
at91sam7s_clear_int(uint32_t mask)
{
    sil_wrw_mem((void *)(TADR_AIC_BASE + TOFF_AIC_ICCR), mask);	
}

/*
 * 充哈み妥滇のチェック
 */
Inline bool_t
at91sam7s_probe_int(uint32_t mask)
{
    return((sil_rew_mem((void *)(TADR_AIC_BASE + TOFF_AIC_IPR)) & mask) == mask);
}

/*
 * カ〖ネル弹瓢箕のログ叫蜗脱の介袋步
 */
Inline void
at91sam7s_init_uart(void)
{
    uint32_t baud = ((MCK * 10) / (BAUDRATE * 16));
    uint32_t brgr;

    /*
     *  at91sam7s_putc が材墙になるようにUARTを介袋步
     */
    brgr = baud / 10U;
    if((baud % 10U) >= 5U){
        brgr = (baud / 10U) + 1;
    }
    sil_wrw_mem((void*)(TADR_PIO_BASE+TOFF_PIO_PDR), TOFF_PIO_PDR_VAL);
    sil_wrw_mem((void*)(TADR_DBGU_BASE+TOFF_US_IDR), 0xFFFFFFFFU);
    sil_wrw_mem((void*)(TADR_DBGU_BASE+TOFF_US_CR), US_RSTRX|US_RSTTX|US_RXDIS|US_TXDIS);
    sil_wrw_mem((void*)(TADR_DBGU_BASE+TOFF_US_BRGR), brgr);
    sil_wrw_mem((void*)(TADR_DBGU_BASE+TOFF_US_MR), 4U<<9U);
    sil_wrw_mem((void*)(TADR_DBGU_BASE+TOFF_US_CR), US_TXEN|US_RXEN);
}

/*
 *  UARTからのポ〖リング叫蜗
 */
Inline void
at91sam7s_putc(char_t c)
{
	while (!(sil_rew_mem((void*)(TADR_DBGU_BASE+TOFF_US_CSR)) & US_TXEMPTY));
	sil_wrw_mem((void*)(TADR_DBGU_BASE+TOFF_US_THR), c);
}

/*
 * 姜位借妄
 */
Inline void
at91sam7s_exit(void)
{    
}
     
#endif /* TOPPPERS_MACRO_ONLY */


#endif /* TOPPERS_AT91SAM7S_H */