📄 hal.h
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//---------------------------------------------------------------------------
//Copyright (C) 2006, Freescale Semiconductor, Inc. All Rights Reserved.
// THIS SOURCE CODE, AND ITS USE AND DISTRIBUTION, IS SUBJECT TO THE TERMS
// AND CONDITIONS OF THE APPLICABLE LICENSE AGREEMENT
//--------------------------------------------------------------------------
//
// File: hal.h
// Header file for platform specific SDIO WLAN functions
//------------------------------------------------------------------------------
#ifndef CFSD_NDHAL_H
#include "wb_types.h"
#include "umi.h"
//
// HAL register definitions.
//
#define HAL_SDIO_FUNCTION_0 (0)
#define HAL_SDIO_FUNCTION_1 (1)
// SDIO CIS base and length.
#define HAL_MAX_CIS_LENGTH (0x100)
#define HAL_CARD_TYPE (2) /* SDIO card */
// SDIO CIA registers.
#define HAL_ADDR_cccr_io_enable (2)
#define HAL_ADDR_cccr_io_abort (6)
#define HAL_ADDR_cccr_bus_interface_control (7)
#define HAL_ADDR_fbr_io_block_size_func1 (0x110)
// Default setting of I/O enable register.
#define HAL_DEFAULT_io_enable (2)
// Bit definition of I/O abort register.
#define HAL_BIT_io_abort_reset (3)
// Bit mask of bus interface control register.
#define HAL_MASK_busifctrl_bus_width (0x03)
// SDIO card control registers.
#define HAL_ADDR_watchdog_status (0x00E)
#define HAL_ADDR_interrupt_host_to_arm (0x00F)
#define HAL_ADDR_interrput_arm_to_host (0x013)
#define HAL_ADDR_interrput_arm_to_host_ex (0x014)
#define HAL_ADDR_interrupt_enable_arm_to_host (0x017)
#define HAL_ADDR_interrupt_enable_arm_to_host_ex (0x018)
#define HAL_ADDR_mailbox_semaphore_0 (0x01C)
#define HAL_ADDR_mailbox_semaphore_1 (0x01D)
#define HAL_ADDR_mailbox_semaphore_2 (0x01E)
// Bit mask of semaphore registers.
#define HAL_MASK_mailbox_semaphore (0x03)
// Value to set or clear semaphore register for SDIO card.
#define HAL_SEMAPHORE_HOST_SET (0x01)
#define HAL_SEMAPHORE_HOST_CLEAR (0x00)
// Bit definitions of interrupt register.
#define HAL_BIT_interrupt_power (0) // bit 0 is power up req. from host
#define HAL_BIT_interrupt_reset_request (0) // to arm, reset req. arm to host
#define HAL_BIT_interrupt_message_bootloader (1)
#define HAL_BIT_interrupt_rx_data0 (2)
#define HAL_BIT_interrupt_rx_data1 (3)
#define HAL_BIT_interrupt_rx_data2 (4)
#define HAL_BIT_interrupt_rx_data3 (5)
#define HAL_BIT_interrupt_tx_data0 (6)
#define HAL_BIT_interrupt_tx_data1 (7)
#define HAL_MASK_interrupt_data (0xFC)
#define HAL_MASK_interrupt_arm_to_host (0xFF)
// Bit mask for interrupt status.
#define HAL_INT_MASK_MSG(x) (((x) >> HAL_BIT_interrupt_message_bootloader) & 0x01)
#define HAL_INT_MASK_RESET(x) (((x) >> HAL_BIT_interrupt_reset_request) & 0x01)
#define HAL_INT_MASK_RX_BUF(x) (((x) >> HAL_BIT_interrupt_rx_data0) & 0x0F)
#define HAL_INT_MASK_TX_BUF(x) (((x) >> HAL_BIT_interrupt_tx_data0) & 0x03)
//
// HAL memory definitions.
//
// SDIO card IMEM base and size.
#define HAL_IMEM_BASE (0x4000)
#define HAL_IMEM_SIZE (0x2000)
#define HAL_IMEM_RX_BUFFER_HEAD (1600)
// Mailbox base and size.
#define HAL_MAILBOX_BASE (0x2000)
#define HAL_MAILBOX_SIZE (0x0800)
#define HAL_IMEM_MAILBOX_SPACE (0x2800)
// Mailbox semaphore.
#define HAL_MAILBOX_0 (0)
#define HAL_MAILBOX_1 (1)
#define HAL_MAILBOX_2 (2)
#define HAL_SEMAPHORE_DELAY (5)
//#define HAL_SEMAPHORE_TIMEOUT (100000) // (1000)
#define HAL_SEMAPHORE_TIMEOUT (100) // (1000)
// Transfer DWORD/BYTE count to BYTE/DWORD count.
#define HAL_DWORDS_TO_BYTES(x) ((x) << 2)
#define HAL_BYTES_TO_DWORDS(x) (((x) + 3) >> 2)
// Maximum number of Tx, Rx buffer.
#define HAL_MAX_TX_BUF_NUM 2
#define HAL_MAX_RX_BUF_NUM 4
// Maximum number of REQ MAN/DBG message buffer.
#define HAL_MAX_REQ_MAN_BUF_NUM 4
#define HAL_MAX_REQ_DBG_BUF_NUM 4
#define HAL_REQ_MAN_QUEUE_SIZE 16
// size of TX internal packet queues
#define HAL_TX_QUEUE_LEN 32
// SDIO clock rates to use in active vs. asleep modes
#define HAL_SDIO_MAX_CLOCK (25000000UL)
#define HAL_SDIO_SLOW_CLOCK (400000UL)
//
// HAL new data types.
//
// Message direction and message type.
typedef USHORT MSG_DIRECTION;
typedef USHORT MSG_TYPE;
// HAL state.
typedef enum
{
HAL_STOPPED,
HAL_READY_TO_DOWNLOAD_1ST,
HAL_AWAITING_BOOT_MAGIC,
HAL_READY_TO_DOWNLOAD_NTH,
HAL_DOWNLOADING,
HAL_STARTING,
HAL_AWAITING_CHI_MAGIC,
HAL_RUNNING
} HAL_STATE;
// HAL power state.
typedef enum
{
HAL_PS_AWAKE,
HAL_PS_ASLEEP,
HAL_PS_WAKING
} HAL_POWER_STATE;
#pragma pack(push,4)
// HAL download structure.
typedef struct
{
ULONG ulCPU; /* The CPU to which code is currently being downloaded. */
ULONG ulOffset; /* Current offset into download image. */
ULONG ulLength; /* Length of image being downloaded. */
PUCHAR paucImage; /* Pointer to image data. */
ULONG ulAddrXferArea; /* Address of code transfer buffer. */
ULONG ulSizeXferArea; /* Capacity of transfer buffer. */
} HAL_DOWNLOAD, * PHAL_DOWNLOAD;
// HAL buffer descriptor.
typedef struct
{
ULONG ulBufAddr; /* The address of buffer on Target. */
ULONG ulBufLen; /* The buffer length. */
PUCHAR pulocalAddr; /* Actual address. */
BOOLEAN boBufAvail; /* Buffer available flag. */
} HAL_BUF_DES, * PHAL_BUF_DES;
// HAL card host interface structure.
typedef struct
{
ULONG ulN; /* The capacity of the circular message */ /* buffers between Host and Target. */
ULONG ulAddrReqResHead; /* Offsets into Target memory of the head */
ULONG ulAddrReqResTail; /* and tail of REQ and IND message queue. */
ULONG ulAddrReqResQ; /* Offset of message queue. */
ULONG ulAddrCfmIndHead;
ULONG ulAddrCfmIndTail;
ULONG ulAddrCfmIndQ;
ULONG ulReqResTail; /* Locally maintained value of the ReqRes tail index, */
ULONG ulCfmIndHead; /* CfmInd head index and */
ULONG ulCfmIndTail; /* CfmInd tail index. */
} HAL_CHI, * PHAL_CHI;
// HAL card status struture.
typedef struct
{
USHORT usCardType; /* 1: CF, 2: SDIO */
USHORT usMACFirmwareVersion;
UCHAR aucUWAFirmwareVersion[2];
USHORT usSiliconVersion;
ULONG ulIRQNumber;
ULONG ulMemoryBase;
ULONG ulMemoryLength;
} HAL_CARD_STATUS, * PHAL_CARD_STATUS;
// HAL CIS structure.
typedef struct
{
ULONG ulCISLength;
UCHAR ucCIS[HAL_MAX_CIS_LENGTH];
} HAL_CIS, * PHAL_CIS;
// HAL read/write register structure.
typedef struct
{
ULONG ulRegAddr;
ULONG ulRegValue;
} HAL_RW_REG, * PHAL_RW_REG;
struct _END_CONTEXT;
// HAL context.
typedef struct
{
struct _END_CONTEXT *psAdapter; /* Pointer to the Adapter context. */
HAL_STATE eState; /* State of the HAL block. */
HAL_POWER_STATE ePowerState; /* Device power state. */
PUCHAR pucBase; /* Mapped device memory base. */
ULONG ulLocalPage; /* Memory page number. */
HAL_CHI sCHI; /* CFHI message passing structure. */
HAL_DOWNLOAD sDownload; /* Active download structure. */
ULONG ulDownloadCount; /* Count of CPUs that have had an image downloaded. */
/* 10k shadow pool mapped to IMEM and Mailbox for Tx buffer and REQ message. */
UCHAR ucShadowPool0[32*8]; /*for 32byte alignment for tx/rx */
UCHAR ucShadowPool[HAL_IMEM_MAILBOX_SPACE];
ULONG ulReqManMsgNum; /* Number of REQ MAN message. */
HAL_BUF_DES sReqManMsgBuf[HAL_MAX_REQ_MAN_BUF_NUM];
ULONG ulReqManMsgRsvdQHead; /* REQ MAN message reserved queue head. */
ULONG ulReqManMsgRsvdQTail; /* REQ MAN message reserved queue tail. */
ULONG ulReqDbgMsgNum; /* Number of REQ DBG message. */
HAL_BUF_DES sReqDbgMsgBuf[HAL_MAX_REQ_DBG_BUF_NUM];
BOOLEAN boTxReqMsgFlag; /* Flag to trace whether REQ message stuck. */
ULONG ulTxRxBufConfig; /* Tx/Rx buffer configuration index. */
ULONG ulTxRxBufSize; /* Size of Tx/Rx buffer. */
ULONG ulTxBufNum; /* Number of Tx buffer on Target. */
HAL_BUF_DES sTxBuf[HAL_MAX_TX_BUF_NUM];
ULONG ulTxBufferIndex; /* Index of the next Tx buffer. */
ULONG ulRxBufNum; /* Number of Rx buffer on Target. */
ULONG aulRxBufferAddr[HAL_MAX_RX_BUF_NUM];
ULONG ulRxBufferIndex; /* Index of the next Rx buffer. */
ULONG ulInterruptStatus; /* Interrupt status */
HAL_CARD_STATUS sCardStatus; /* Card status for TestUtility. */
HAL_CIS sCIS; /* CIS for TestUtility. */
HAL_RW_REG sRWReg; /* Read/write register for TestUtility. */
BOOLEAN boNDISRequestedReset;
BOOLEAN boSupport4BitMode; // true to allow 4 bit mode, else 1 bit mode
BOOLEAN boSupportBlockMode; // true to allow block transfers, else byte only
ULONG ulBlockSize; // if using block mode, sets block size in bytes
ULONG ulMaxBlockNumber; // max # of blocks per CMD53 transfer
ULONG ulMaxByteNumber; // in byte mode, max number of bytes per CMD53
ULONG ulMaxClockFreq; // restrict clock frequency
// prioritized queues for pending TX packets
PNDIS_PACKET apTxQueues[4][HAL_TX_QUEUE_LEN];
ULONG ulQueueHeads[4];
ULONG ulQueueTails[4];
} HAL_CONTEXT, * PHAL_CONTEXT;
#pragma pack(pop)
//
// HAL high level functions.
//
VOID vHALinitReqMessage( IN PHAL_CONTEXT psHAL, IN UMI_MSG *psMsg );
UMI_MSG * psHALnewReqMessage( IN PHAL_CONTEXT psHAL, IN MSG_TYPE eType );
VOID vHALreturnReqMessage( IN PHAL_CONTEXT psHAL, IN UMI_MSG *psMsg );
BOOLEAN boHALsendMessage( IN PHAL_CONTEXT psHAL, IN UMI_MSG * psMsg );
VOID vHALreceiveMessage( IN PHAL_CONTEXT psHAL );
VOID vHALbeginDownload( IN PHAL_CONTEXT psHAL, IN ULONG ulCPU );
VOID vHALcontinueDownload( IN PHAL_CONTEXT psHAL );
BOOLEAN boHALdownload( IN PHAL_CONTEXT psHAL, IN BOOLEAN boStart );
VOID vHALstart( IN PHAL_CONTEXT psHAL );
VOID vHALstop( IN OUT PHAL_CONTEXT psHAL );
VOID vHALinitTxRxBuffer( IN PHAL_CONTEXT psHAL );
VOID vHALflushTxQueues( struct _END_CONTEXT *psAdapter );
BOOLEAN bHAL_PickAndSendPacket(struct _END_CONTEXT *psAdapter);
int iHALsendPacket(IN PHAL_CONTEXT psHAL,IN PNDIS_PACKET psPktDesc,IN uint32 ulPriority);
VOID vHALsendComplete( IN PHAL_CONTEXT psHAL, IN ULONG ulBitmapTxBuf );
VOID vHALreceivePacket( IN PHAL_CONTEXT psHAL, IN ULONG ulBitmapRxBuf );
VOID vHALinterruptDevice( IN PHAL_CONTEXT psHAL, IN ULONG ulIntMask, IN ULONG ulIntOffset );
VOID vHALenableInterrupt( IN PHAL_CONTEXT psHAL );
VOID vHALdisableInterrupt( IN PHAL_CONTEXT psHAL );
VOID vHALIsr( OUT PBOOLEAN InterruptRecognized, OUT PBOOLEAN QueueMiniportHandleInterrupt,IN NDIS_HANDLE MiniportAdapterContext );
VOID vHALGetCardInfo( IN PHAL_CONTEXT psHAL );
ULONG ulHALcheckActivity( IN PHAL_CONTEXT psHAL );
VOID vHALwakeupDevice( IN PHAL_CONTEXT psHAL );
VOID vHALSetMaxClockRate(IN PHAL_CONTEXT psHAL, uint32 u32FrequencyInHz);
VOID vHALPSTimer( IN PVOID pvSystemSpecific1, IN NDIS_HANDLE psFuncContext, IN PVOID pvSystemSpecific2, IN PVOID pvSystemSpecific3 );
VOID vHALsendGetStatsReq( IN PHAL_CONTEXT psHAL );
VOID vHALsendClearUwaStatsReq( IN PHAL_CONTEXT psHAL );
VOID vHALsendGetGenStatsReq( IN PHAL_CONTEXT psHAL );
VOID vHALsendClearGenStatsReq( IN PHAL_CONTEXT psHAL );
VOID vHALsendScanReq( IN PHAL_CONTEXT psHAL );
VOID vHALsendDisconnectReq( IN PHAL_CONTEXT psHAL, IN USHORT usReason );
VOID vHALsendGetRssiReq( IN PHAL_CONTEXT psHAL, IN IEEE_ADDR * psMacAddr );
VOID vHALsendSetKeyReq( IN PHAL_CONTEXT psHAL, IN UMI_SET_KEY * psSetKey );
VOID vHALsendClearKeyReq( IN PHAL_CONTEXT psHAL, IN UMI_CLEAR_KEY * psClearKey );
VOID vHALsendPowerOffReq( IN PHAL_CONTEXT psHAL );
VOID vHALsendGetMibReq( IN PHAL_CONTEXT psHAL, IN MIB_ID u16MibId );
VOID vHALsendSetMibReq( IN PHAL_CONTEXT psHAL, IN MIB_ID u16MibId, IN MIB_VALUE * puValue );
VOID vHALsendPowerModeReq( IN PHAL_CONTEXT psHAL, IN BOOLEAN boEnablePS );
VOID vHALsendActivateReq( IN PHAL_CONTEXT psHAL, IN UMI_ACTIVATE * psActivate );
VOID vHALstartMACconfiguration( IN PHAL_CONTEXT psHAL );
VOID vHALMessageHandler( IN PHAL_CONTEXT psHAL, IN UMI_MSG * psMsg );
VOID vHALreadCardCIS( IN PHAL_CONTEXT psHAL, IN PVOID pData, IN ULONG ulLength );
VOID vHALhandleInterrupt(IN NDIS_HANDLE MiniportAdapterContext);
#define CFSD_NDHAL_H
#endif // CFSD_NDHAL_H
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