bsp_cfg.h

来自「mx27 f14v2 源代码。包括ADS板上诸多驱动的源码。」· C头文件 代码 · 共 232 行

//
// Copyright (c) Microsoft Corporation.  All rights reserved.
//
//
// Use of this source code is subject to the terms of the Microsoft end-user
// license agreement (EULA) under which you licensed this SOFTWARE PRODUCT.
// If you did not accept the terms of the EULA, you are not authorized to use
// this source code. For a copy of the EULA, please see the LICENSE.RTF on your
// install media.
//
//------------------------------------------------------------------------------
//
// Copyright (C) 2004-2006, Freescale Semiconductor, Inc. All Rights Reserved.
// THIS SOURCE CODE, AND ITS USE AND DISTRIBUTION, IS SUBJECT TO THE TERMS
// AND CONDITIONS OF THE APPLICABLE LICENSE AGREEMENT
//
//------------------------------------------------------------------------------
//
// File:  bsp_cfg.h
//
// This file contains system constant specific for MX27 ADS board.
//
//------------------------------------------------------------------------------
#ifndef __BSP_CFG_H__
#define __BSP_CFG_H__

//------------------------------------------------------------------------------
//
//  Define:  BSP_DEVICE_PREFIX
//
//  Prefix used to generate device name for bootload/KITL
//
#define BSP_DEVICE_PREFIX           "MX27"      // Device name prefix


//------------------------------------------------------------------------------
// Clock Configuration Settings
//------------------------------------------------------------------------------
//------------------------------------------------------------------------------
// BSP_REF_32KHZ_FREQ specifies frequency of osc crystal used for the MX27.
// It must be one of the following:
//  BSP_REF_FREQ_32768KHZ
//  BSP_REF_FREQ_32000KHZ
//  BSP_SRC_FREQ_38400HZ
//
#define BSP_SRC_FREQ_32768HZ           32768   // Supported by EVB
#define BSP_SRC_FREQ_32000HZ           32000   // Supported by ADS
#define BSP_SRC_FREQ_38400HZ           38400	// not support

#define MX27_ADS_BSP
// #define MX27_EVB_BSP
//
//  The definition of BSP_REF_32KHZ_FREQ is now an environment setting.
//  If it is not set as environment variable, then sources.cmn will set value 32000
//

//------------------------------------------------------------------------------
// GPT Clock Source
#define BSP_OEM_GPT_CLOCK_SRC       GPT_TCTL_CLKSOURCE_PERCLK1
// Target system timer freq in Hz
#define OEM_CLOCK_FREQ			    3325000     

#define OEM_TICKS_1MS               (OEM_CLOCK_FREQ / 1000)             // 1ms in ticks
#define RESCHED_PERIOD              1                                   // Reschedule ms
#define RESCHED_INCREMENT           (RESCHED_PERIOD * OEM_TICKS_1MS)    // Reschedule
#define OEM_TICKS_MARGIN            400

//------------------------------------------------------------------------------
// PBC Board Configuration
//------------------------------------------------------------------------------
#define BSP_PBC_IRQ                     IRQ_GPIO_PC_15
#define BSP_PBC_GPIO_PORT               GPIO_PORT_C
#define BSP_PBC_GPIO_PIN                15
#define BSP_PBC_GPIO_LEVEL              GPIO_ICR_HIGH_LEVEL

//------------------------------------------------------------------------------
// USB Board Configuration
//------------------------------------------------------------------------------
#define BSP_USB_IRQ                 IRQ_GPIO_PA_6   // LD0 Always not usesd as interrupt on Bono, Remap it to USB IRQ

//------------------------------------------------------------------------------
// Fast Ethernet IRQ Configuration
//------------------------------------------------------------------------------
#define BSP_FEC_IRQ              IRQ_GPIO_PA_7

//------------------------------------------------------------------------------
// Low Battery IRQ Configuration
//------------------------------------------------------------------------------
#define BSP_LOW_BAT_IRQ              IRQ_GPIO_PA_8

//------------------------------------------------------------------------------
// External UART IRQ Configuration
//------------------------------------------------------------------------------
#define BSP_XUART_IRQ              IRQ_GPIO_PA_9

//------------------------------------------------------------------------------
// External Ethernet IRQ Board Configuration
//------------------------------------------------------------------------------
#define BSP_CS8900_IRQ              IRQ_GPIO_PA_15

//------------------------------------------------------------------------------
// DSHC/SDIO IRQ Configuration
//------------------------------------------------------------------------------
#define BSP_SDHC_MS_IRQ              IRQ_GPIO_PC_10

//------------------------------------------------------------------------------
// CCTL1_2 IRQ Configuration
//------------------------------------------------------------------------------
#define BSP_CCTL_IRQ                 IRQ_GPIO_PA_11   


//------------------------------------------------------------------------------
// PMIC Board Configuration
//------------------------------------------------------------------------------
#define BSP_PMIC_IRQ            IRQ_GPIO_PC_14
#define BSP_PMIC_CSPI_FREQ      4000000 // 4 MHz (limited by ADS signal quality)
#define BSP_PMIC_CSPI_PORT      1

#define BSP_PMIC_GPIO_PORT      GPIO_PORT_C
#define BSP_PMIC_GPIO_PIN       14

#define BSP_PMIC_CPU_REGULATOR  SW1A
#define BSP_PMIC_NORMAL_VOLT    0x17    // MC13783 code for 1.475V
#define BSP_PMIC_STANDBY_VOLT   0x4     // MC13783 code for 1.0V
#define BSP_PMIC_LOWSPEED_VOLT  0x12    // MC13783 code for 1.350V        

//------------------------------------------------------------------------------
// BSP_DISPLAY_CONTROLLER specifies which display controller is used. 
// It must be one of the following :
//     DISPLAY_CONTROLLER_LCDC
//     DISPLAY_CONTROLLER_SLCDC
//
//-----------------------------------------------------------------------------
#define DISPLAY_CONTROLLER_LCDC     0
#define DISPLAY_CONTROLLER_SLCDC    1

#ifndef BSP_SLCDC
#define BSP_DISPLAY_CONTROLLER      DISPLAY_CONTROLLER_LCDC 
#else
#define BSP_DISPLAY_CONTROLLER      DISPLAY_CONTROLLER_SLCDC
#endif

//------------------------------------------------------------------------------
// LCD Panel Configuration to support IOCTL_HAL_QUERY_DISPLAYSETTINGS
//------------------------------------------------------------------------------
#ifdef VGA_DISPLAY
#define BSP_PREF_DISPLAY_WIDTH      640
#define BSP_PREF_DISPLAY_HEIGHT     480
#define BSP_PREF_DISPLAY_BPP        16
#define BSP_PIXEL_CLOCK_FREQ        18432000 
#else
#define BSP_PREF_DISPLAY_WIDTH      240
#define BSP_PREF_DISPLAY_HEIGHT     320
#define BSP_PREF_DISPLAY_BPP        16
#define BSP_PIXEL_CLOCK_FREQ        6800000 // 4.5-6.8MHz
#endif

//------------------------------------------------------------------------------
// Debug OUTPUT
// DEBUG_PORT specifies which UART we use for debug serial port. It must be one
// of the following :
//     DBG_UART1
//     DBG_SC16C652
//------------------------------------------------------------------------------
#define DBG_UART1               1
#define DBG_SC16C652            2

#ifdef BSP_EXT_DBG_PORT
#define DEBUG_PORT              DBG_SC16C652
#else
#define DEBUG_PORT              DBG_UART1
#endif

//------------------------------------------------------------------------------
// I2C Port
// The I2C_PORT specifies the which I2C device will be used.  It must be
// one of the following :
//     CAM_I2C_PORT
//     USB_I2C_PORT
//------------------------------------------------------------------------------
#define CAM_I2C_PORT            L"I2C1:"
#define USB_I2C_PORT            L"I2C2:"

//------------------------------------------------------------------------------
// Boot configuration data storage
// BOOTCFG_STORAGE specifies what storage is used for storage boot configuration
// data.
// It must be one of the following :
//     BOOTCFG_STORAGE_NAND
//     BOOTCFG_STORAGE_EEPROM
//------------------------------------------------------------------------------
#define BOOTCFG_STORAGE_NAND    0
#define BOOTCFG_STORAGE_EEPROM  1

//#define BOOTCFG_STORAGE       BOOTCFG_STORAGE_NAND
#define BOOTCFG_STORAGE         BOOTCFG_STORAGE_EEPROM

//------------------------------------------------------------------------------
#define SYSINTR_USBOTG          (SYSINTR_FIRMWARE+2)


//------------------------------------------------------------------------------
// BSP_DMA_CH_AUDIO_TX specifies the dmac channel used for audio tx.
// BSP_DMA_CH_AUDIO_RX specifies the dmac channel used for audio rx.
// BSP_DMA_CH_SDHC_TX specifies the dmac channel used for SDHC tx.
// BSP_DMA_CH_SDHC_RX specifies the dmac channel used for SDHC tx.
// BSP_DMA_CH_FIRI_TX specifies the dmac channel used for FIRI tx.
// BSP_DMA_CH_FIRI_RX specifies the dmac channel used for FIRI rx.
// Notes:
// must be one of the following :
//     0      (lowest priority)
//      ....
//     15     (highest priority)
// 
//------------------------------------------------------------------------------
#define BSP_DMA_CH_AUDIO_TX          15
#define BSP_DMA_CH_AUDIO_RX          14
#define BSP_DMAC_CH_SDHC1_TX         13
#define BSP_DMAC_CH_SDHC1_RX         12
#define BSP_DMAC_CH_SDHC2_TX         11
#define BSP_DMAC_CH_SDHC2_RX         10
#define BSP_DMAC_CH_SDHC3_TX         9
#define BSP_DMAC_CH_SDHC3_RX         8
#define BSP_DMAC_CH_ATA_TX           7
#define BSP_DMAC_CH_ATA_RX           6

#define BSP_DMAC_SDHC_BUFF_SIZE     (0x00020000) 
#define BSP_DMAC_ATA_BUFF_SIZE      (0x00020000) 

#endif // __BSP_CFG_H__