ne2000.h

ARM得编程实例。很经典。在win ce5.0环境下的编程实例

/*******************************************************************
             
*******************************************************************/

#ifndef NE2000_H
#define NE2000_H

/**********************************************************
 *
 * Define Network Interface Controller Registers    
 * 
 **********************************************************/

#define CR      0x00    /* Command Register */

/* Page 0 read register */

#define CLDA0   0x01    /* Current Local DMA Address 0 */
#define CLDA1   0x02    /* Current Local DMA Address 1 */
#define BNDRY   0x03    /* Boundary Pointer */
#define TSR     0x04    /* Transmit Status Register */
#define NCR     0x05    /* Number of Collisions Register */
#define FIFO    0x06    /* FIFO */
#define ISR     0x07    /* Interupt Status Register */
#define CRDA0   0x08    /* Current Remote DMA Address 0 */
#define CRDA1   0x09    /* Current Remote DMA Address 1 */
#define RES1    0x0A    /* Reserved */
#define RES2    0x0B    /* Reserved */
#define RSR     0x0C    /* Receive Status Register */
#define CNTR0   0x0D    /* Tally Counter 0 (Frame Alignment Errors) */
#define CNTR1   0x0E    /* Tally Counter 1 (CRC Errors) */
#define CNTR2   0x0F    /* Tally Counter 2 (Missed Packet Errors) */

/* Page 0 write register */

#define PSTART  0x01    /* Page Start Register */
#define PSTOP   0x02    /* Page Stop Register */
#define TPSR    0x04    /* Transmit Page Start Address */
#define TBCR0   0x05    /* Transmit Byte Count Register 0 */
#define TBCR1   0x06    /* Transmit Byte Count Register 1 */
#define RSAR0   0x08    /* Remote Start Address Register 0 */
#define RSAR1   0x09    /* Remote Start Address Register 1 */
#define RBCR0   0x0A    /* Remote Byte Count Register 0 */
#define RBCR1   0x0B    /* Remote Byte Count Register 1 */
#define RCR     0x0C    /* Receive Configuration Register */
#define TCR     0x0D    /* Transmit Configuration Register */
#define DCR     0x0E    /* Data Configuration Register */
#define IMR     0x0F    /* Interrupt Mask Register */

/* Page 1 register */

#define PAR0    0x01    /* Physical Address Register 0 */
#define PAR1    0x02    /* Physical Address Register 1 */
#define PAR2    0x03    /* Physical Address Register 2 */
#define PAR3    0x04    /* Physical Address Register 3 */
#define PAR4    0x05    /* Physical Address Register 4 */
#define PAR5    0x06    /* Physical Address Register 5 */
#define CURR    0x07    /* Current Page Register */
#define MAR0    0x08    /* Multicast Address Register 0 */
#define MAR1    0x09    /* Multicast Address Register 1 */
#define MAR2    0x0A    /* Multicast Address Register 2 */
#define MAR3    0x0B    /* Multicast Address Register 3 */
#define MAR4    0x0C    /* Multicast Address Register 4 */
#define MAR5    0x0D    /* Multicast Address Register 5 */
#define MAR6    0x0E    /* Multicast Address Register 6 */
#define MAR7    0x0F    /* Multicast Address Register 7 */

/* Other registers */

#define NIC_DATA        0x10  /* Data Register for I/O port mode */
#define NIC_RESET       0x18  /* Reset Register */

/**********************************************************
 *   Send and Receive Areas Defines
 *
 *    8-bit mode - wasting ram but saving I/O count,
 *    Send     6 * 256-byte (1.5K , address: 4000-45ff)
 *    receive  26 * 256-byte (6.5K, address: 4600-5fff)
 **********************************************************/

/* Send Area 1.5K, enough for 1 maximum ethernet packets*/
#define TXSTART_INIT    0x40

/* Receive Area 6.5K, enough for at least 4 maximum ethernet packets*/
#define RXSTART_INIT	0x46
#define RXSTOP_INIT	    0x60

#define RXSTOP_ADDRESS  (unsigned short)(RXSTOP_INIT<<8)
#define RXSTART_ADDRESS (unsigned short)(RXSTART_INIT<<8)

/*********************************************************************
*
* ISR(Interrupt Status Register) Bits Definition
*
*********************************************************************/
#define ISR_RST 7
#define ISR_RDC 6
#define ISR_CNT 5
#define ISR_OVW 4
#define ISR_TXE 3
#define ISR_RXE 2
#define ISR_PTX 1
#define ISR_PRX 0

/*********************************************************************
*
*  RTL Register Initialization Values
*
*********************************************************************/
/* RCR : accept broadcast packets and packets destined to this MAC*/
/*         drop short frames and receive errors*/
#define RCR_INIT                0x04

/* TCR : default transmit operation - CRC is generated */
#define TCR_INIT                0x00

/* DCR : allows send packet to be used for packet retreival*/
/*         FIFO threshold: 8-bits (works)*/
/*         8-bit transfer mode*/
#define DCR_INIT                0x58

/* IMR : interrupt enabled for receive and overrun events*/
#define IMR_INIT                0x13

#define MIN_ETHERNET_FRAME_LEN  46
#define MAX_ETHERNET_FRAME_LEN  1500

/* Location of items int the packet header */
#define PACKET_STATUS   0x00
#define PACKET_NEXTBLK  0x01
#define PACKET_LENLOW   0x02
#define PACKET_LENHIGH  0x03

#endif /* NE2000_H */