cs8900.h.svn-base

三星arm2440与cs8900的以太网驱动

/*******************************************************************************
*   File Name: 
					cs89x0.h
*   Description:
				    cs89x0 ethernet controler.	
*   Copyright:
      Copyright (c) 2003 LONICOM, Incorporated and its licensors. All Rights 
    Reserved. LONICOM Proprietary. Export of this technology or software is 
    regulated by the P.R.C Government. Diversion contrary to P.R.C law 
    prohibited.

*   Change History:
*   Date          Author      Release     Description
	2008/03/05    wangguofeng   0.1         create
*******************************************************************************/

/*******************************************************************************
                                Include Files
*******************************************************************************/
#ifndef _CS8900_H_
#define _CS8900_H_

#include "osekernel.h"
#include "dsm.h"

/******************************************************************************/
/***************************macros and structures******************************/
#define ETHER_DEBUG         3
#define ETHER_TEST			0 
#define ETHER_NOT_YET       0

#define ETHER_PKT_MAX       1514
#define SEND_Q_MAX          64
#define ETHER_PRN_SIZE 	    128

#define DOWN                0
#define UP                  1

#define ETHER_INT_BIT       5 
#define MSG_WAKEUP          0
#define ETHER_ADDR_LEN      6
#define BUS_NOT_RDY         (-1)

#define SEND_MSG_TRIGGER    0x1
#define SEND_INT_TRIGGER    0x2
#define BUF_INT_TRIGGER     0x4
#define RECV_INT_TRIGGER    0x8

/* tcpip call back prototype. */
typedef void (* rxEnqueue)(dsm_item_type *data); 
typedef void (* rxMsgSend)(void); 
typedef void (* ifStateNotify)(LC_BYTE state); 

/* enthernet interface statistic. */
struct ifStatistic
{
	LC_DWORD dwSendFrame;
    LC_DWORD dwSendByte;
    LC_DWORD dwRecvFrame;
    LC_DWORD dwRecvByte;
    LC_DWORD dwSendError; 
    LC_DWORD dwSendQueueFull;
    LC_DWORD dwSendQueueMax;  
    LC_DWORD dwSendPktTooLong;
    LC_DWORD dwRecvPktTooLong;
    LC_DWORD dwRecvPktTooShort;
    LC_DWORD dwInvalidRecvFrame;
    LC_DWORD dwDsmMallocFailed;      
    
    #if ETHER_DEBUG
    LC_DWORD dwEtherDsmLogicError;
    LC_DWORD dwTcpipDsmLogicError;
    LC_DWORD dwSendInt;
    LC_DWORD dwRecvInt;
    LC_DWORD dwBuffInt;
    #endif
    
    #if ETHER_TEST
    LC_DWORD dwRecvQueueFull;
    LC_DWORD dwRecvQueueMax;           
    #endif 
    
    LC_DWORD dwRxMiss;
    LC_DWORD dwTxCol;
};

#if ETHER_TEST
struct	etherHeader 
{
	LC_BYTE	etherDesHost[ETHER_ADDR_LEN];
	LC_BYTE	etherSrcHost[ETHER_ADDR_LEN];
	LC_WORD	etherType;
};

/* temp defined for test. */
#define BIG_ENDIAN  0xff
#define BYTE_ORDER LITTLE_ENDIAN

struct ip 
{
#if BYTE_ORDER == LITTLE_ENDIAN 
	LC_BYTE	ip_hl:4,		/* header length */
		    ip_v:4;			/* version */
#endif
#if BYTE_ORDER == BIG_ENDIAN 
	LC_BYTE	ip_v:4,			/* version */
		    ip_hl:4;		/* header length */
#endif
	LC_BYTE	ip_tos;			/* type of service */
	LC_WORD	ip_len;			/* total length */
	LC_WORD	ip_id;			/* identification */
	LC_WORD	ip_off;			/* fragment offset field */
	LC_BYTE	ip_ttl;			/* time to live */
	LC_BYTE	ip_p;			/* protocol */
	LC_WORD	ip_sum;			/* checksum */
	LC_DWORD ip_src, ip_dst;	/* source and dest address */
};

struct tcphdr 
{
	LC_WORD	    th_sport;		/* source port */
	LC_WORD	    th_dport;		/* destination port */
	LC_DWORD	th_seq;			/* sequence number */
	LC_DWORD	th_ack;			/* acknowledgement number */
	
#if BYTE_ORDER == LITTLE_ENDIAN 
	LC_BYTE	    th_x2:4,		/* (unused) */
		        th_off:4;		/* data offset */
#endif

#if BYTE_ORDER == BIG_ENDIAN 
	LC_BYTE	    th_off:4,		/* data offset */
		        th_x2:4;		/* (unused) */
#endif

	LC_BYTE	th_flags;

	LC_WORD	th_win;			/* window */
	LC_WORD	th_sum;			/* checksum */
	LC_WORD	th_urp;			/* urgent pointer */
};

struct udphdr 
{
	LC_WORD	uh_sport;		/* source port */
	LC_WORD	uh_dport;		/* destination port */
	LC_WORD	uh_ulen;		/* udp length */
	LC_WORD	uh_sum;			/* udp checksum */
};

#endif /* ETHER_TEST */

/******************************************************************************/
/*********************ethernet controller registers****************************/
/* 16 bit bus. */
#define CS8900_BASE 0x19000300
#define CS8900_REG  LC_WORD
#define CS8900_OFF  2

#define CHIP_EISA_ID_SIG 0x630E

#define RX_FRAME_PORT   0x0000
#define TX_FRAME_PORT   RX_FRAME_PORT
#define TX_CMD_PORT	    0x0004
#define TX_NOW		    0x0000       /*  Tx packet after   5 bytes copied */
#define TX_AFTER_381	0x0040       /*  Tx packet after 381 bytes copied */
#define TX_AFTER_ALL	0x00c0       /*  Tx packet after all bytes copied */
#define TX_LEN_PORT	    0x0006
#define ISQ_PORT	    0x0008
#define ADD_PORT	    0x000A
#define DATA_PORT	    0x000C

#define PP_ISAIOB           0x0020	/*  IO base address */
#define PP_CS8900_ISAINT    0x0022	/*  ISA interrupt select */
#define PP_CS8920_ISAINT    0x0370	/*  ISA interrupt select */
#define PP_CS8900_ISADMA    0x0024	/*  ISA Rec DMA channel */
#define PP_CS8920_ISADMA    0x0374	/*  ISA Rec DMA channel */
#define PP_ISASOF           0x0026	/*  ISA DMA offset */
#define PP_DmaFrameCnt      0x0028	/*  ISA DMA Frame count */
#define PP_DmaByteCnt       0x002A	/*  ISA DMA Byte count */
#define PP_CS8900_ISAMemB   0x002C	/*  Memory base */
#define PP_CS8920_ISAMemB   0x0348  /*  */

#define ISQ_RxEvent     0x04
#define ISQ_TxEvent     0x08
#define ISQ_BufEvent    0x0C
#define ISQ_RxMissEvent 0x10
#define ISQ_TxColEvent  0x12
#define ISQ_EventMask   0x3F