spi_configure.c

在SPI 平台优化好的G.711代码,保证好用

//////////////////////////////////////////////////////////////////////////////
//
//    Title:        spi_configure.c
//
//    Description:  Application-specific DSP MIPS configuration.
//
//    Copyright:    Copyright (C) 2006 by Stream Processors, Inc.
//                  This program is provided under the terms of the SPI
//                  end-user license agreement (EULA). This program may only
//                  be used in a manner explicitly specified in the EULA,
//                  which includes limitations on copying, modifying,
//                  redistribution and warranties.  Unauthorized use of this
//                  program is sctrictly prohibited.  You may obtain a copy of
//                  the EULA from www.streamprocessors.com. 
//
//    Source Info:  $File: //depot/swdev/rapidev-098/software/demo/g711/spi_configure.c $
//                  $Revision: #1 $
//
//////////////////////////////////////////////////////////////////////////////

#if	defined(SPI_TARGET_DEVICE)

#include "spi_common.h"

// Define the entry point of each StreamC task in this configuration.
extern int dspmain(void);

// Define the MIPS clock speed on the target.
#define MIPS_CLOCK_SPEED     (250000000)    /* 250 MHz clock */

// Define the number of tasks, fifo ids and sizes, app buffer ids and sizes.
#define	NUM_DSP_MIPS_TASKS	1
#define	TASK0_NUM_MSG_FIFOS     2
#define	TASK0_NUM_APP_BUFFERS   1
#define	NUM_OVERLAY_LISTS       0
#define	SPI_CMD_FIFO_ID		0
#define	SPI_STATUS_FIFO_ID	1
#define	SPI_APPBUF_ID		0
#define	SPI_CMD_FIFO_SIZE_IN_WORDS	(4096)
#define	SPI_STATUS_FIFO_SIZE_IN_WORDS	(4096)
#define	SPI_APPBUF_SIZE_IN_WORDS	(4096)

// Define the total number of bytes desired for all StreamC task dynamic memory pools.
// The StreamC task memory pool is used for the task stack and dynamic memory needs during runtime.
// This number must be the summation of of all task stacks and memory pools as defined in the
// Spi_Config structure below.
#define	TASK0_STACK_SIZE_IN_BYTES	(64 * 1024)
#define	TASK0_MEMPOOL_SIZE_IN_BYTES	(1024 * 1024)
#define NUM_BYTES_IN_APPLICATION_MEMPOOL (TASK0_STACK_SIZE_IN_BYTES + TASK0_MEMPOOL_SIZE_IN_BYTES)

// Define where DSP MIPS output messages to stdout and stderr are redirected.
// Must be one of the following:
//     SPI_UART_0       -- send output to UART 0
//     SPI_UART_1       -- send output to UART 1
//     SPI_UART_2       -- send output to UART 2
//     SPI_UART_3       -- send output to UART 3
//     SPI_SYSTEM_MIPS  -- send output as a message to System MIPS
#define STDOUT_LOCATION                  (SPI_SYSTEM_MIPS)
#define STDERR_LOCATION                  (SPI_SYSTEM_MIPS)
// Define where DSP MIPS monitor output is redirected.
// Must be a UART or SPI_DISABLE_DEBUG_MONITOR; cannot be SPI_SYSTEM_MIPS.
#define DSP_MIPS_DEBUG_MONITOR_LOCATION  (SPI_UART_1)

// Define the DSP MIPS run-time configuration.
// System MIPS uses this structure to configure the memory of the communications block
// before DSP MIPS starts execution.
__attribute__ ((section (".initconfig"))) SPI_STREAMC_CONFIG Spi_Config =
{
   "SPI DSP MIPS Configuration",             // configuration name
   NUM_DSP_MIPS_TASKS,                       // number of StreamC tasks in this configuration
   {                                         // start of task desciptors
      {                                      // task 0 descriptor
         "DSP MIPS main task",               // task name
         "dspmain",                          // task entry name
         (void (*)(void))&dspmain,           // task entry function
         TASK0_STACK_SIZE_IN_BYTES,          // task stack size
         TASK0_MEMPOOL_SIZE_IN_BYTES,        // task dynamic memory pool size in bytes
         TASK0_NUM_MSG_FIFOS,                // number of message FIFOs used by this task
         {                                   // start message FIFO descriptors
            {                                // FIFO ID 0
               "Command FIFO",               // FIFO name
               SPI_CMD_FIFO_ID,              // FIFO ID
               SPI_SYSTEM_MIPS_TO_DSP_MIPS,  // FIFO direction
               SPI_CMD_FIFO_SIZE_IN_WORDS,   // FIFO size
            },                               // end of FIFO ID 0
            {                                // FIFO ID 1
               "Status FIFO",                // FIFO name
               SPI_STATUS_FIFO_ID,           // FIFO ID
               SPI_DSP_MIPS_TO_SYSTEM_MIPS,  // FIFO direction
               SPI_STATUS_FIFO_SIZE_IN_WORDS, // FIFO size
            },                               // end of FIFO ID 1
         },                                  // end message FIFO desciptors
         TASK0_NUM_APP_BUFFERS,              // number of application buffers
         {                                   // start application buffer descriptors
            {                                // application buffer 0
               "Mempool Buffer",             // application buffer name
               SPI_APPBUF_ID,                // application buffer ID
               SPI_APPBUF_SIZE_IN_WORDS,     // number of 32-bit data words in buffer
            },                               // end application buffer 0
         },                                  // end of application buffer descriptors 
      },                                     // end of task 0 descriptor
   },                                        // end of task descriptors
   NUM_OVERLAY_LISTS,                        // number of overlay lists in this configuration
   {                                         // start of overlay lists
      {                                      // overlay list descriptor 
         0,                                  // number of app buffers that will be overlayed
         {                                   // array of application IDs
             0,
         },                                  // end of array of application IDs
         {                                   // array of buffer IDs
             0,
         },                                  // end of array of buffer IDs
      },                                     // end of overlay list descriptor 
   }                                         // end of overlay lists
};


//!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!
// DO NOT MODIFY CODE AFTER THIS COMMENT!
//!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!

//  The DSP MIPS dynamic memory pool also includes space for the LRF (256KB for SP-16)
//  and for the internal runtime system overhead (ca. 80KB).
//  This memory pool is NOT used for message FIFO's or application buffers.  
#define LRF_OVERHEAD_PER_TASK             (16 * 16384)   // assuming SP-16
#define INTERNAL_OVERHEAD_PER_TASK        (80000)
#define TOTAL_INTERNAL_OVERHEAD_PER_TASK  (LRF_OVERHEAD_PER_TASK + INTERNAL_OVERHEAD_PER_TASK)  

#define TOTAL_BYTES_IN_MEMPOOL       (NUM_BYTES_IN_APPLICATION_MEMPOOL + (NUM_DSP_MIPS_TASKS * TOTAL_INTERNAL_OVERHEAD_PER_TASK))

// Storage for all StreamC task memory pools 
unsigned char  Mips_Dsp_App_Memory_Pool[TOTAL_BYTES_IN_MEMPOOL];

unsigned int Mips_Clock_Speed = MIPS_CLOCK_SPEED;
unsigned int Spi_Lanes    = SPI_LANES;

// Internal runtime data structure
INTERNAL_INIT_INFO  Internal_Data = 
{
   TOTAL_BYTES_IN_MEMPOOL,
   Mips_Dsp_App_Memory_Pool,
   STDOUT_LOCATION,
   STDERR_LOCATION,
   DSP_MIPS_DEBUG_MONITOR_LOCATION,
};

#endif	// defined(SPI_TARGET_DEVICE)

// end of spi_configure.c