mftphy2500rf.c

2500驱动

// PATABLE (0 dBm output power)
  #include <C8051F330.h>
  #include "..\mft.h"
  #include "..\public.h"	
  #include "regssrf04.h"
  #include "mftPHY2500.h"
   	 

//#define Debug
extern void SYS_Delay10us(uchar d10us);
#define  PHYDATALENGTH    10//APP_DATA_LENGTH-2

  uchar   packetLength,bufferlength;
 uchar NCS_CHOOSE ;
void CC2500_NCS_CHOOS(unsigned char choose)
{
  if(NCS_CHOOSE)
   {
     if(choose)
        CC2500_NCS1 =1;
	 else 
	    CC2500_NCS1 =0;  
   }
   else 
   {
     if(choose)
        CC2500_NCS0 =1;
	 else 
	    CC2500_NCS0 =0; 
   } 
}
// Macro used for communication data polling and wait on the SPI bus
void SPI_WAIT()
{
    while(!SPIF);
    SPIF=0;
}
void Spi_Switch()
{
				SPIEN = 0x00;
			//	 SPI0CKR=0;
     SPI0CFG   = 0x40;       //CKPHA=0  CKPOL=0
    	SPIEN = 0x01;
    	//SYS_Delay10us(1);
}
void Spi_Restore()
{
			SPIEN = 0x00; 
		//	SPI0CKR=0x01;
			SPI0CFG   = 0x70;       //CKPHA=1  CKPOL=1
    	SPIEN = 0x01;
}
//----------------------------------------------------------
// Macro to reset the CCxxx0 and wait for it to be ready
void POWER_UP_RESET_CC0(void)
{
	#if defined Debug
	return;
	#endif

    CC2500_SCK=1;
    CC2500_MOSI=0;
    
    CC2500_NCS_CHOOS(0);
    while (CC2500_MISO);
     CC2500_NCS_CHOOS(1);
    SYS_Delay10us(10);
   // RESET_CCxxx0();
    CC2500_NCS_CHOOS(0);
  	while (CC2500_MISO);
  	SPI0DAT = CCxxx0_SRES;
  	SPI_WAIT();
  	while (CC2500_MISO) ;
   CC2500_NCS_CHOOS(1);
}

//-------------------------------------------------------------------------------------------------------
//  void halSpiWriteReg(uchar addr, uchar value)
//
//  DESCRIPTION:
//      Function for writing to a single CCxxx0 register
//
//  ARGUMENTS:
//      uchar addr
//          Address of a specific CCxxx0 register to accessed.
//      uchar value
//          Value to be written to the specified CCxxx0 register.
//-------------------------------------------------------------------------------------------------------
void halSpiWriteReg(unsigned char addr,unsigned char value) {
   // DisableMouseInt() ;
   	#if defined Debug
	return;
	#endif
    Spi_Switch()  ;    //CKPHA=0  CKPOL=0    
    CC2500_NCS_CHOOS(0);
    while (CC2500_MISO);
    SPI0DAT = addr;
    SPI_WAIT();
    SPI0DAT = value;
    SPI_WAIT();
    CC2500_NCS_CHOOS(1);
    Spi_Restore();       //CKPHA=1  CKPOL=1
   // EnableMouseInt();
}// halSpiWriteReg

//-------------------------------------------------------------------------------------------------------
//  Global Variables

//在SmartRF Studio中取数格式: 0x@VH@,   //@RN@    @Rd@

// Chipcon
// Product = CC2500
// Chip version = E
// Crystal accuracy = 40 ppm
// X-tal frequency = 26 MHz
// RF output power = 0 dBm
// RX filterbandwidth = 232.000000 kHz
// Deviation = 38.000000 kHz
// Datarate = 10.000000 kbps
// Modulation = (0) 2-FSK
// Manchester enable = (1) Manchester enabled
// RF Frequency = 2433.000000 MHz
// Channel spacing = 199.950000 kHz
// Channel number = 0
// Sync mode = (3) 30/32 sync word bits detected
// Format of RX/TX data = (0) Normal mode, use FIFOs for RX and TX
// CRC operation = (1) CRC calculation in TX and CRC check in RX enabled
// Forward Error Correction = (0) FEC disabled
// Length configuration = (1) Variable length packets, packet length configured by the first received uchar after sync word.
// Packetlength = 255
// Preamble count = (2)  4 bytes
// Append status = 1
// Address check = (2) Address check, 0 (0x00) broadcast
// FIFO autoflush = 0
// Device address = 0
// GDO0 signal selection = ( 6) Asserts when sync word has been sent / received, and de-asserts at the end of the packet
// GDO2 signal selection = ( 7)



//-------------------------------------------------------------------------------------------------------
//  void halSpiWriteBurstReg(uchar addr, uchar *buffer, uchar count)
//
//  DESCRIPTION:
//      This function writes to multiple CCxxx0 register, using SPI burst access.
//
//  ARGUMENTS:
//      uchar addr
//          Address of the first CCxxx0 register to be accessed.
//      uchar *buffer
//          Array of bytes to be written into a corresponding range of
//          CCxx00 registers, starting by the address specified in _addr_.
//      uchar count
//          Number of bytes to be written to the subsequent CCxxx0 registers.
//-------------------------------------------------------------------------------------------------------
void halSpiWriteBurstReg(unsigned char  addr, unsigned char  *buffer, unsigned char  count) {
    unsigned char  i;
    //DisableMouseInt() ;
    	#if defined Debug
	return;
	#endif
    Spi_Switch()   ;   //CKPHA=0  CKPOL=0
    CC2500_NCS_CHOOS(0);
    while (CC2500_MISO);
    SPI0DAT = addr | WRITE_BURST;
    SPI_WAIT();
    for (i = 0; i < count; i++) {
        SPI0DAT = buffer[i];
        SPI_WAIT();
    }
     CC2500_NCS_CHOOS(1);
    Spi_Restore();       //CKPHA=1  CKPOL=1
   // EnableMouseInt();
}// halSpiWriteBurstReg

//-------------------------------------------------------------------------------------------------------
//  void halSpiStrobe(uchar strobe)
//
//  DESCRIPTION:
//      Function for writing a strobe command to the CCxxx0
//
//  ARGUMENTS:
//      uchar strobe
//          Strobe command
//-------------------------------------------------------------------------------------------------------
void halSpiStrobe(unsigned char  strobe) {
//  DisableMouseInt() ;
	#if defined Debug
	return;
	#endif
	   Spi_Switch()  ;    //CKPHA=0  CKPOL=0   
    CC2500_NCS_CHOOS(0);
    while (CC2500_MISO);
    SPI0DAT = strobe;
    SPI_WAIT();

    CC2500_NCS_CHOOS(1);   
    Spi_Restore();       //CKPHA=1  CKPOL=1
}// halSpiStrobe

//-------------------------------------------------------------------------------------------------------
//  void halRfSendPacket(uchar *txBuffer, UINT8 size)
//
//  DESCRIPTION:
//      This function can be used to transmit a packet with packet length up to 63 bytes.
//      To use this function, GD00 must be configured to be asserted when sync word is sent and
//      de-asserted at the end of the packet => halSpiWriteReg(CCxxx0_IOCFG0, 0x06);
//      The function implements polling of GDO0. First it waits for GD00 to be set and then it waits
//      for it to be cleared.
//
//  ARGUMENTS:
//      uchar *txBuffer
//          Pointer to a buffer containing the data that are going to be transmitted
//
//      UINT8 size
//          The size of the txBuffer
//-------------------------------------------------------------------------------------------------------
/*void halRfSendPacket(uchar *txBuffer, uchar size)  {
	#if defined Debug
	return;
	#endif

    halSpiWriteBurstReg(CCxxx0_TXFIFO, txBuffer, size);
    halSpiStrobe(CCxxx0_STX); //begin send data
  

}// halRfSendPacket
*/
//-------------------------------------------------------------------------------------------------------
//  uchar halSpiReadStatus(uchar addr)
//
//  DESCRIPTION:
//      This function reads a CCxxx0 status register.
//
//  ARGUMENTS:
//      uchar addr
//          Address of the CCxxx0 status register to be accessed.
//
//  RETURN VALUE:
//      uchar
//          Value of the accessed CCxxx0 status register.
//-------------------------------------------------------------------------------------------------------
unsigned char  halSpiReadStatus(unsigned char  addr) {
	
    unsigned char x;
    	#if defined Debug
	return 0;
	#endif
   // DisableMouseInt();
    Spi_Switch()  ;    //CKPHA=0  CKPOL=0
    CC2500_NCS_CHOOS(0);
    while (CC2500_MISO);
    SPI0DAT = (addr | READ_BURST);
    SPI_WAIT();
    SPI0DAT = 0;
    SPI_WAIT();
    x = SPI0DAT;
    CC2500_NCS_CHOOS(1);
    Spi_Restore();       //CKPHA=1  CKPOL=1
   // EnableMouseInt();
    return x;
}// halSpiReadStatus

//-------------------------------------------------------------------------------------------------------
//  uchar halSpiReadReg(uchar addr)
//
//  DESCRIPTION:
//      This function gets the value of a single specified CCxxx0 register.
//
//  ARGUMENTS:
//      uchar addr
//          Address of the CCxxx0 register to be accessed.
//
//  RETURN VALUE:
//      uchar
//          Value of the accessed CCxxx0 register.
//-------------------------------------------------------------------------------------------------------
unsigned char  halSpiReadReg(unsigned char  addr) {

    uchar x;
    		#if defined Debug
	return 0;
	#endif
    Spi_Switch()  ;    //CKPHA=0  CKPOL=0
    CC2500_NCS_CHOOS(0);
    while (CC2500_MISO);
    SPI0DAT = (addr | READ_SINGLE);
    SPI_WAIT();

    SPI0DAT = 0;
    SPI_WAIT();
    x = SPI0DAT;
    CC2500_NCS_CHOOS(1);
    Spi_Restore();       //CKPHA=1  CKPOL=1
    return x;
}// halSpiReadReg

//-------------------------------------------------------------------------------------------------------
//  void halSpiReadBurstReg(uchar addr, uchar *buffer, uchar count)
//
//  DESCRIPTION:
//      This function reads multiple CCxxx0 register, using SPI burst access.
//
//  ARGUMENTS:
//      uchar addr
//          Address of the first CCxxx0 register to be accessed.
//      uchar *buffer
//          Pointer to a uchar array which stores the values read from a
//          corresponding range of CCxxx0 registers.
//      uchar count
//          Number of bytes to be written to the subsequent CCxxx0 registers.
//-------------------------------------------------------------------------------------------------------
void halSpiReadBurstReg(uchar addr, uchar *buffer, uchar count) {
	
    uchar  i;
    	#if defined Debug
	return;
	#endif
  //  DisableMouseInt();
    Spi_Switch()  ;    //CKPHA=0  CKPOL=0
    CC2500_NCS_CHOOS(0);
    while (CC2500_MISO);
  //  EA =0 ;
    SPI0DAT = (addr | READ_BURST);
    SPI_WAIT();
    for (i = 0; i < count; i++) {
        SPI0DAT = 0;
        SPI_WAIT();
        buffer[i] = SPI0DAT;
    }
  //  EA =1 ;
     CC2500_NCS_CHOOS(1);
    Spi_Restore();       //CKPHA=1  CKPOL=1
    // EnableMouseInt();
}// halSpiReadBurstReg

//-------------------------------------------------------------------------------------------------------
//  BOOL halRfReceivePacket(uchar *rxBuffer, UINT8 *length)
//
//  DESCRIPTION:
//      This function can be used to receive a packet of variable packet length (first uchar in the packet
//      must be the length uchar). The packet length should not exceed the RX FIFO size.
//      To use this function, GD00 must be configured to be asserted when sync word is sent and
//      de-asserted at the end of the packet => halSpiWriteReg(CCxxx0_IOCFG0, 0x06);
//      Also, APPEND_STATUS in the PKTCTRL1 register must be enabled.
//      The function implements polling of GDO0. First it waits for GD00 to be set and then it waits
//      for it to be cleared.
//      After the GDO0 pin has been de-asserted, the RXBYTES register is read to make sure that there
//      are bytes in the FIFO. This is because the GDO signal will indicate sync received even if the
//      FIFO is flushed due to address filtering, CRC filtering, or packet length filtering.
//
//  ARGUMENTS:
//      uchar *rxBuffer
//          Pointer to the buffer where the incoming data should be stored
//      UINT8 *rssi
//          Pointer to a variable containing the rssi of the buffer where the incoming data should be
//          stored. After this function returns, that variable holds the packet RSSI.
//
//  RETURN VALUE:
//      BOOL
//          TRUE:   CRC OK
//          FALSE:  CRC NOT OK
//-------------------------------------------------------------------------------------------------------
/*uchar halRfReceivePacket(uchar *rxBuffer, uchar *rssi) {
  
 while(!GDO2_PIN)
	   {  
	   _nop_();
	   }
//Tick^=1;
	#if defined Debug
	return 1;
	#endif
  bufferlength = halSpiReadStatus(CCxxx0_RXBYTES);
  if (bufferlength) 
  {
        // Read data from RX FIFO and store in rxBuffer
      packetLength = halSpiReadReg(CCxxx0_RXFIFO);
			if((packetLength!=0)&&(packetLength<=PHYDATALENGTH))
			{
	         halSpiReadBurstReg(CCxxx0_RXFIFO,rxBuffer,packetLength+2);
					 *rssi=rxBuffer[packetLength];  
				   return (packetLength);
			}
	}
	 return FALSE;
	}*/