📄 mftphy2500.c
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/*********************************************************************
*
* MFTAMAC layer
*
*********************************************************************
* FileName: mftPHY2500.c
* Dependencies:
* Processor: c51
* Company: chengdu MFT, Inc.
*
* Software License Agreement:All right reserved
*
*
* Author Date Comment
*~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
* 2/25/06 Rel 0.1
********************************************************************/
#include "c8051f330.h"
#include "..\mft.h"
#include "..\public.h"
#include "mftPHY2500.h"
#include "regssrf04.h"
extern void delayms(uchar delayms);
unsigned char code rfSettingsLong[34] = {
//500k
//-------------------------------------------------------------
/* 0x0D, //FSCTRL1 Frequency synthesizer control.
0x00, //FSCTRL0 Frequency synthesizer control.
0x10, //FREQ2 Frequency control word, high byte:0x436M~463M//Channel:0-139
0xA7, //FREQ1 Frequency control word, middle byte.
0x62, //FREQ0 Frequency control word, low byte.
0x0E, //MDMCFG4 Modem configuration.//filter channel bandwidth:0x0e->0x5e:812khz->325khz
0x3B, //MDMCFG3 Modem configuration.
0x73, //MDMCFG2 Modem configuration.
0xC2, //MDMCFG1 Modem configuration.
0xF8, //MDMCFG0 Modem configuration.*/
//250k
0x0A, //FSCTRL1 Frequency synthesizer control.
0x00, //FSCTRL0 Frequency synthesizer control.
0x10, //FREQ2 Frequency control word, high byte:0x436M~463M//Channel:0-139
0xA7, //FREQ1 Frequency control word, middle byte.
0x62, //FREQ0 Frequency control word, low byte.
0x2d, //MDMCFG4 Modem configuration.//filter channel bandwidth:0x0e->0x5e:812khz->325khz
0x3B, //MDMCFG3 Modem configuration.
0x73, //MDMCFG2 Modem configuration.
0xA2, //MDMCFG1 Modem configuration.
0xF8, //MDMCFG0 Modem configuration.
//------------------------------------------------------------------
FIRSTCHAN, //CHANNR Channel number.
0x00, // DEVIATN Modem deviation setting (when FSK modulation is enabled).
0xB6, // FREND1 Front end RX configuration.
0x10, // FREND0 Front end RX configuration.
0x09,// MCSM0 Main Radio Control State Machine configuration. 0x18->0x09
0x1D, // FOCCFG Frequency Offset Compensation Configuration.
0x1C, // BSCFG Bit synchronization Configuration.
0xC7, // AGCCTRL2 AGC control.
0x00, // AGCCTRL1 AGC control.
0xB2, // AGCCTRL0 AGC control.
0xEA, // FSCAL3 Frequency synthesizer calibration.//0xea->ca dialble pump charge
0x2A, // FSCAL2 Frequency synthesizer calibration.
0x00, // FSCAL1 Frequency synthesizer calibration.
0x1F, // FSCAL0 Frequency synthesizer calibration.
0x59, // FSTEST Frequency synthesizer calibration.
0x88, // TEST2 Various test settings.
0x31, // TEST1 Various test settings.
0x09, // TEST0 Various test settings.
0x41, // IOCFG2 GDO2 output pin configuration.
0x2E, // IOCFG0D GDO0 output pin configuration. Refer to SmartRF?Studio User Manual for detailed pseudo register explanation.
0x06, // PKTCTRL1 Packet automation control.
0x45, // PKTCTRL0 Packet automation control.
0x00, // ADDR Device address.
20 // PKTLEN Packet length.
};
uchar code paTableLong[1] = {0xC0}; //{10DB};//0DB
// Chipcon
// Product = CC2500
// Chip version = E
unsigned char code rfSettings[34] = {
0x07, //FSCTRL1 Frequency synthesizer control.
0x00, //FSCTRL0 Frequency synthesizer control.
0x5C, //FREQ2 Frequency control word, high uchar. //0x5d->0x5b->5cBASE frequence:2386M jc 2006/7/29 channel Nuber:71~255->0~255
0x93, //FREQ1 Frequency control word, middle uchar.
0xB1, //FREQ0 Frequency control word, low uchar.
0x2D, //MDMCFG4 Modem configuration. //0x2d:Filter Width:541K jc:2007/4/7
0x3B, //MDMCFG3 Modem configuration.
0x73, //MDMCFG2 Modem configuration.
0xA2, //MDMCFG1 Modem configuration. //0xa2->:channel wideth 200k
0xF8, //MDMCFG0 Modem configuration. //0xf8->
//-----------------------------------------------------------
FIRSTCHAN, //CHANNR Channel number.
0x01, //DEVIATN Modem deviation setting (when FSK modulation is enabled).
0xB6, //FREND1 Front end RX configuration.
0x10, //FREND0 Front end RX configuration.
0x09, //MCSM0 Main Radio Control State Machine configuration.//jc 0x09->0x29.tx/rx->idle cb
0x1D, //FOCCFG Frequency Offset Compensation Configuration.
0x1C, //BSCFG Bit synchronization Configuration.
0xC7, //AGCCTRL2 AGC control.
0x00, // AGCCTRL1 AGC control. //new parameter
0xB2, //AGCCTRL0 AGC control.
0xEA, // FSCAL3 Frequency synthesizer calibration.//0xea->ca dialble pump charge
0x0A, //FSCAL2 Frequency synthesizer calibration.
0x00, // FSCAL1 Frequency synthesizer calibration.//new parameter
0x11, //FSCAL0 Frequency synthesizer calibration.
0x59, //FSTEST Frequency synthesizer calibration.
0x88, //TEST2 Various test settings.
0x31, //TEST1 Various test settings.
0x0B, //TEST0 Various test settings.
0x41, //IOCFG2 GDO2 output pin configuration.//0x47->0x46
0x30, //IOCFG0D GDO0 output pin configuration. Refer to SmartRF?Studio User Manual for detailed pseudo register explanation.0x06->0x2e->0X30 high impedance->cca
0x06, //PKTCTRL1 Packet automation control.0x06->0x86 :pqt->0x0e.crc error flush rxbuffer
0x45, //PKTCTRL0 Packet automation control.0x05->0x45.Packet whiten.
0x00, //ADDR Device address.
20, //PKTLEN Packet length.
};
//----------------------------------------------------------------------------------------
uchar code paTable[1] = {0xFE}; //{0xFF:1.5DB,0XFE:0DB};//0DB
extern void delayms(uchar dms);
extern MAC_STATE macState;
static uchar PHYChannel;
extern uchar SynTickBak;
extern bit APPJobFlag;
extern uchar timeCnt;
uchar PhySendFlag ;
void halRfWriteRfSettings(void) {
uchar upartnum;
upartnum = halSpiReadStatus(CCxxx0_PARTNUM);
if(upartnum==0x80)//cc2500
{
halSpiWriteReg(CCxxx0_FSCTRL1, rfSettings[FSCTRL1]);
halSpiWriteReg(CCxxx0_FSCTRL0, rfSettings[FSCTRL0]);
halSpiWriteReg(CCxxx0_FREQ2, rfSettings[FREQ2]);
halSpiWriteReg(CCxxx0_FREQ1, rfSettings[FREQ1]);
halSpiWriteReg(CCxxx0_FREQ0, rfSettings[FREQ0]);
halSpiWriteReg(CCxxx0_MDMCFG4, rfSettings[MDMCFG4]);
halSpiWriteReg(CCxxx0_MDMCFG3, rfSettings[MDMCFG3]);
halSpiWriteReg(CCxxx0_MDMCFG2, rfSettings[MDMCFG2]);
halSpiWriteReg(CCxxx0_MDMCFG1, rfSettings[MDMCFG1]);
halSpiWriteReg(CCxxx0_MDMCFG0, rfSettings[MDMCFG0]);
halSpiWriteReg(CCxxx0_CHANNR, rfSettings[CHANNR]);
halSpiWriteReg(CCxxx0_DEVIATN, rfSettings[DEVIATN]);
halSpiWriteReg(CCxxx0_FREND1, rfSettings[FREND1]);
halSpiWriteReg(CCxxx0_FREND0, rfSettings[FREND0]);
halSpiWriteReg(CCxxx0_MCSM0 , rfSettings[MCSM0 ]);
halSpiWriteReg(CCxxx0_FOCCFG, rfSettings[FOCCFG]);
halSpiWriteReg(CCxxx0_BSCFG, rfSettings[BSCFG]);
halSpiWriteReg(CCxxx0_AGCCTRL2,rfSettings[AGCCTRL2]);
halSpiWriteReg(CCxxx0_AGCCTRL0,rfSettings[AGCCTRL0]);
halSpiWriteReg(CCxxx0_FSCAL3, rfSettings[FSCAL3]);
halSpiWriteReg(CCxxx0_FSCAL2, rfSettings[FSCAL2]);
halSpiWriteReg(CCxxx0_FSCAL0, rfSettings[FSCAL0]);
halSpiWriteReg(CCxxx0_FSTEST, rfSettings[FSTEST]);
halSpiWriteReg(CCxxx0_TEST2, rfSettings[TEST2]);
halSpiWriteReg(CCxxx0_TEST1, rfSettings[TEST1]);
halSpiWriteReg(CCxxx0_TEST0, rfSettings[TEST0]);
halSpiWriteReg(CCxxx0_IOCFG2, rfSettings[IOCFG2]);
halSpiWriteReg(CCxxx0_IOCFG0, rfSettings[IOCFG0]);
halSpiWriteReg(CCxxx0_PKTCTRL1,rfSettings[PKTCTRL1]);
halSpiWriteReg(CCxxx0_PKTCTRL0,rfSettings[PKTCTRL0]);
halSpiWriteReg(CCxxx0_ADDR, rfSettings[ADDR]);
halSpiWriteReg(CCxxx0_PKTLEN, rfSettings[PKTLEN]);
PhySendFlag= paTable[0] ;
}
else
{
halSpiWriteReg(CCxxx0_FSCTRL1, rfSettingsLong[FSCTRL1]);
halSpiWriteReg(CCxxx0_FSCTRL0, rfSettingsLong[FSCTRL0]);
halSpiWriteReg(CCxxx0_FREQ2, rfSettingsLong[FREQ2]);
halSpiWriteReg(CCxxx0_FREQ1, rfSettingsLong[FREQ1]);
halSpiWriteReg(CCxxx0_FREQ0, rfSettingsLong[FREQ0]);
halSpiWriteReg(CCxxx0_MDMCFG4, rfSettingsLong[MDMCFG4]);
halSpiWriteReg(CCxxx0_MDMCFG3, rfSettingsLong[MDMCFG3]);
halSpiWriteReg(CCxxx0_MDMCFG2, rfSettingsLong[MDMCFG2]);
halSpiWriteReg(CCxxx0_MDMCFG1, rfSettingsLong[MDMCFG1]);
halSpiWriteReg(CCxxx0_MDMCFG0, rfSettingsLong[MDMCFG0]);
halSpiWriteReg(CCxxx0_CHANNR, rfSettingsLong[CHANNR]);
halSpiWriteReg(CCxxx0_DEVIATN, rfSettingsLong[DEVIATN]);
halSpiWriteReg(CCxxx0_FREND1, rfSettingsLong[FREND1]);
halSpiWriteReg(CCxxx0_FREND0, rfSettingsLong[FREND0]);
halSpiWriteReg(CCxxx0_MCSM0 , rfSettingsLong[MCSM0 ]);
halSpiWriteReg(CCxxx0_FOCCFG, rfSettingsLong[FOCCFG]);
halSpiWriteReg(CCxxx0_BSCFG, rfSettingsLong[BSCFG]);
halSpiWriteReg(CCxxx0_AGCCTRL2,rfSettingsLong[AGCCTRL2]);
halSpiWriteReg(CCxxx0_AGCCTRL1,rfSettingsLong[AGCCTRL1]);//add new parameter
halSpiWriteReg(CCxxx0_AGCCTRL0,rfSettingsLong[AGCCTRL0]);
halSpiWriteReg(CCxxx0_FSCAL3, rfSettingsLong[FSCAL3]);
halSpiWriteReg(CCxxx0_FSCAL2, rfSettingsLong[FSCAL2]);
halSpiWriteReg(CCxxx0_FSCAL1, rfSettingsLong[FSCAL1]);//add new parameter
halSpiWriteReg(CCxxx0_FSCAL0, rfSettingsLong[FSCAL0]);
halSpiWriteReg(CCxxx0_FSTEST, rfSettingsLong[FSTEST]);
halSpiWriteReg(CCxxx0_TEST2, rfSettingsLong[TEST2]);
halSpiWriteReg(CCxxx0_TEST1, rfSettingsLong[TEST1]);
halSpiWriteReg(CCxxx0_TEST0, rfSettingsLong[TEST0]);
halSpiWriteReg(CCxxx0_IOCFG2, rfSettingsLong[IOCFG2]);
halSpiWriteReg(CCxxx0_IOCFG0, rfSettingsLong[IOCFG0]);
halSpiWriteReg(CCxxx0_PKTCTRL1,rfSettingsLong[PKTCTRL1]);
halSpiWriteReg(CCxxx0_PKTCTRL0,rfSettingsLong[PKTCTRL0]);
halSpiWriteReg(CCxxx0_ADDR, rfSettingsLong[ADDR]);
halSpiWriteReg(CCxxx0_PKTLEN, rfSettingsLong[PKTLEN]);
PhySendFlag= paTableLong[0] ;
}
halSpiWriteBurstReg(CCxxx0_PATABLE,&PhySendFlag, 1); //change to
//EnableInterrupts;
}// halRfWriteRfSettings
/**********************************************************************
* 函数: void PHYIntInit()
* 功能：2500 中断初始化 外部中断1
**********************************************************************/
void PHYIntInit()
{
IT1 =1 ; //边缘触发//边缘触发
IT0 =1;
IE1 = 0;
IE0 = 0;
IT01CF = 0x67; //INT1 P0.7，INT1 P0.6,Low level
EX1 =1; //外部中断1允许位
EX0 =1;
}
//calibrate 2500 pll clock
void PHYCalibratePLL(void)
{
halSpiStrobe(CCxxx0_SIDLE);
halSpiStrobe(CCxxx0_SCAL); //calibrate clock
delayms(1);
}
/**********************************************************************
* 函数: void PHYSetChannel(uchar chanNel)
* 功能：设置无线收发器的频道
* 输入：channel 逻辑频道,由RF 无线收发器支持的频道决定.
* 描述：此函数用于在频道扫描或频道冲突时,上层可以改变当前的物理频道
**********************************************************************/
void PHYSetChannel(uchar channel)
{
if(channel<FIRSTCHAN)
channel = FIRSTCHAN;
halSpiStrobe(CCxxx0_SIDLE);
PHYChannel=channel;
halSpiWriteReg(CCxxx0_CHANNR,PHYChannel);
PHYCalibratePLL();
}
/*uchar PHYGetRssi()
{
return halSpiReadStatus(CCxxx0_FREQEST);
}*/
/**********************************************************************
函数: void PHYSetNextChannel(void)
功能：设置无线收发器的频道为下一个频道
输出：如果设置成功，则返回TRUE,否则返回FALSE.
描述：在当前频道的基础上加1，切换到下一个频道,如果下一个频道超出了RF支
持的物理频道的数量,则返回失败,否则设置下一个频道为当前频道,返回TRUE.
**********************************************************************/
void PHYSetNextChannel(void)
{
// return TRUE;
// if((PHYChannel)>=max_channr)
// return FALSE;
halSpiStrobe(CCxxx0_SIDLE);
PHYChannel++;
halSpiWriteReg(CCxxx0_CHANNR,PHYChannel);
PHYCalibratePLL();
}
void PHYSetPHYAddress(uchar PhyAddress)
{
halSpiStrobe(CCxxx0_SIDLE);
halSpiWriteReg(CCxxx0_ADDR, PhyAddress);
}
/**********************************************************************
函数: void PHYSetFirstChannel(void)
功能：设置无线收发器的第一个频道
描述：
**********************************************************************/
void PHYSetFirstChannel(void)
{
// return ;
halSpiStrobe(CCxxx0_SIDLE);
PHYChannel=FIRSTCHAN;
halSpiWriteReg(CCxxx0_CHANNR,PHYChannel);
PHYCalibratePLL();
}
//Clear rx receive bufffer,active 2500 into rx state
/*
void PHYClearRxFIFO()
{
static uchar gdoLowTimes=0;
//---------------------------------------------
if(!GDO2_PIN)//possible 2550 into receive dead state,read rx buffer active it.
{
gdoLowTimes++;
if(gdoLowTimes>2)
{
gdoLowTimes = 0;
halSpiReadReg(CCxxx0_RXFIFO);
halSpiStrobe(CCxxx0_SFRX); //flush rx buffer jc 10.2
}
}
else
{
gdoLowTimes = 0;
}
//---------------------------------------------
}*/
/**********************************************************************
函数: void PHYClearRxBuffer()
功能：clear rx fifo.in case of 2500 buffer error
描述：
**********************************************************************/
/*void PHYClearRxBuffer() {
halSpiReadReg(CCxxx0_RXFIFO);
halSpiStrobe(CCxxx0_SFRX);//clear rx fifo
}*/
/**********************************************************************
函数: void PHYSetTRXState(PHY_TRX_STATE state)
功能: 设置RF 的状态.
输入: state 表示RF 新的状态.接收状态PHY_TRX_RX_ON,发送状态
PHY_TRX_TX_ON,或者关闭状态PHY_TRX_OFF,PHY_TRX_FORCE_OFF.
描述: 无线收发器有三种状态,一是处于接收,二是处于发送,三是处于关闭.在关
闭收发器时,PHY_TRX_FORCE_OFF 表示强制关闭.不管现在是什么状态.⌨️ 快捷键说明
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