mc68hc908jw32.h

motorola jw32 usb 源码

/*** POCR2 - Port Option Control Register 2; 0x0000001B ***/
typedef union {
  byte Byte;
  struct {
    byte PTE2P       :1;                                       /* Pin PTE2 Pullup Enable */
    byte PTE3P       :1;                                       /* Pin PTE3 Pullup Enable */
    byte DPPULLEN    :1;                                       /* D+ Pullup Enable */
    byte PTD2PD      :1;                                       /* Pin PTD2 Pullup Disable */
    byte PTD3PD      :1;                                       /* Pin PTD3 Pullup Disable */
    byte PTD7PD      :1;                                       /* Pin PTD7 Pullup Disable */
    byte             :1; 
    byte             :1; 
  } Bits;
} POCR2STR;
extern volatile POCR2STR _POCR2 @0x0000001B;
#define POCR2                           _POCR2.Byte
#define POCR2_PTE2P                     _POCR2.Bits.PTE2P
#define POCR2_PTE3P                     _POCR2.Bits.PTE3P
#define POCR2_DPPULLEN                  _POCR2.Bits.DPPULLEN
#define POCR2_PTD2PD                    _POCR2.Bits.PTD2PD
#define POCR2_PTD3PD                    _POCR2.Bits.PTD3PD
#define POCR2_PTD7PD                    _POCR2.Bits.PTD7PD

#define POCR2_PTE2P_MASK                1
#define POCR2_PTE3P_MASK                2
#define POCR2_DPPULLEN_MASK             4
#define POCR2_PTD2PD_MASK               8
#define POCR2_PTD3PD_MASK               16
#define POCR2_PTD7PD_MASK               32


/*** IOCR - IRQ Option Register; 0x0000001C ***/
typedef union {
  byte Byte;
  struct {
    byte IRQPD       :1;                                       /* IRQ Pullup Disable */
    byte PTE3IE      :1;                                       /* PTE3 Interrupt Enable */
    byte PTE3IF      :1;                                       /* PTE3 Interrupt Flag */
    byte             :1; 
    byte             :1; 
    byte             :1; 
    byte             :1; 
    byte             :1; 
  } Bits;
} IOCRSTR;
extern volatile IOCRSTR _IOCR @0x0000001C;
#define IOCR                            _IOCR.Byte
#define IOCR_IRQPD                      _IOCR.Bits.IRQPD
#define IOCR_PTE3IE                     _IOCR.Bits.PTE3IE
#define IOCR_PTE3IF                     _IOCR.Bits.PTE3IF

#define IOCR_IRQPD_MASK                 1
#define IOCR_PTE3IE_MASK                2
#define IOCR_PTE3IF_MASK                4


/*** CONFIG2 - Configuration Register 2; 0x0000001D ***/
typedef union {
  byte Byte;
  struct {
    byte URSTD       :1;                                       /* USB Reset Disable Bit */
    byte VREG33D     :1;                                       /* 3.3V USB Regulator Disable Bit */
    byte CLKS        :1;                                       /* Clock source selection Bit */
    byte             :1; 
    byte STOP_RCCLKEN :1;                                      /* RC clock Stop Mode Enable */
    byte STOP_XCLKEN :1;                                       /* Crystal Oscillator Stop Mode Enable */
    byte STOPEN      :1;                                       /* STOP pin output enable */
    byte             :1; 
  } Bits;
} CONFIG2STR;
extern volatile CONFIG2STR _CONFIG2 @0x0000001D;
#define CONFIG2                         _CONFIG2.Byte
#define CONFIG2_URSTD                   _CONFIG2.Bits.URSTD
#define CONFIG2_VREG33D                 _CONFIG2.Bits.VREG33D
#define CONFIG2_CLKS                    _CONFIG2.Bits.CLKS
#define CONFIG2_STOP_RCCLKEN            _CONFIG2.Bits.STOP_RCCLKEN
#define CONFIG2_STOP_XCLKEN             _CONFIG2.Bits.STOP_XCLKEN
#define CONFIG2_STOPEN                  _CONFIG2.Bits.STOPEN

#define CONFIG2_URSTD_MASK              1
#define CONFIG2_VREG33D_MASK            2
#define CONFIG2_CLKS_MASK               4
#define CONFIG2_STOP_RCCLKEN_MASK       16
#define CONFIG2_STOP_XCLKEN_MASK        32
#define CONFIG2_STOPEN_MASK             64


/*** ISCR - IRQ Status and Control Register; 0x0000001E ***/
typedef union {
  byte Byte;
  struct {
    byte MODE        :1;                                       /* IRQ Edge/Level Select Bit */
    byte IMASK       :1;                                       /* IRQ Interrupt Mask Bit */
    byte ACK         :1;                                       /* IRQ Interrupt Request Acknowledge Bit */
    byte IRQF        :1;                                       /* IRQ Flag Bit */
    byte             :1; 
    byte             :1; 
    byte             :1; 
    byte             :1; 
  } Bits;
} ISCRSTR;
extern volatile ISCRSTR _ISCR @0x0000001E;
#define ISCR                            _ISCR.Byte
#define ISCR_MODE                       _ISCR.Bits.MODE
#define ISCR_IMASK                      _ISCR.Bits.IMASK
#define ISCR_ACK                        _ISCR.Bits.ACK
#define ISCR_IRQF                       _ISCR.Bits.IRQF

#define ISCR_MODE_MASK                  1
#define ISCR_IMASK_MASK                 2
#define ISCR_ACK_MASK                   4
#define ISCR_IRQF_MASK                  8


/*** CONFIG1 - Configuration Register 1; 0x0000001F ***/
typedef union {
  byte Byte;
  struct {
    byte COPD        :1;                                       /* COP Disable Bit */
    byte STOP        :1;                                       /* STOP Instruction Enable Bit */
    byte SSREC       :1;                                       /* Short Stop Recovery Bit */
    byte             :1; 
    byte LVIPWRD     :1;                                       /* LVI Power Disable Bit */
    byte LVIRSTD     :1;                                       /* LVI Reset Disable Bit */
    byte LVISTOP     :1;                                       /* LVI Enable in Stop Mode Bit */
    byte COPRS       :1;                                       /* COP rate Select Bit */
  } Bits;
} CONFIG1STR;
extern volatile CONFIG1STR _CONFIG1 @0x0000001F;
#define CONFIG1                         _CONFIG1.Byte
#define CONFIG1_COPD                    _CONFIG1.Bits.COPD
#define CONFIG1_STOP                    _CONFIG1.Bits.STOP
#define CONFIG1_SSREC                   _CONFIG1.Bits.SSREC
#define CONFIG1_LVIPWRD                 _CONFIG1.Bits.LVIPWRD
#define CONFIG1_LVIRSTD                 _CONFIG1.Bits.LVIRSTD
#define CONFIG1_LVISTOP                 _CONFIG1.Bits.LVISTOP
#define CONFIG1_COPRS                   _CONFIG1.Bits.COPRS

#define CONFIG1_COPD_MASK               1
#define CONFIG1_STOP_MASK               2
#define CONFIG1_SSREC_MASK              4
#define CONFIG1_LVIPWRD_MASK            16
#define CONFIG1_LVIRSTD_MASK            32
#define CONFIG1_LVISTOP_MASK            64
#define CONFIG1_COPRS_MASK              128


/*** DC1CR - Data Codec 1 Control Register; 0x00000020 ***/
typedef union {
  byte Byte;
  struct {
    byte RSTTRG0     :1;                                       /* Reset trigger Selection Bit 0 */
    byte RSTTRG1     :1;                                       /* Reset trigger Selection Bit 1 */
    byte MODE        :1;                                       /* Mode selection bit */
    byte INITLOG     :1;                                       /* Initial Logic Definition bit */
    byte PSTART      :1;                                       /* Pulse Generation Enable bit */
    byte             :1; 
    byte             :1; 
    byte DCMEN       :1;                                       /* Data Codec Enable bit */
  } Bits;
  struct {
    byte grpRSTTRG :2;
    byte         :1;
    byte         :1;
    byte         :1;
    byte         :1;
    byte         :1;
    byte         :1;
  } MergedBits;
} DC1CRSTR;
extern volatile DC1CRSTR _DC1CR @0x00000020;
#define DC1CR                           _DC1CR.Byte
#define DC1CR_RSTTRG0                   _DC1CR.Bits.RSTTRG0
#define DC1CR_RSTTRG1                   _DC1CR.Bits.RSTTRG1
#define DC1CR_MODE                      _DC1CR.Bits.MODE
#define DC1CR_INITLOG                   _DC1CR.Bits.INITLOG
#define DC1CR_PSTART                    _DC1CR.Bits.PSTART
#define DC1CR_DCMEN                     _DC1CR.Bits.DCMEN
#define DC1CR_RSTTRG                    _DC1CR.MergedBits.grpRSTTRG

#define DC1CR_RSTTRG0_MASK              1
#define DC1CR_RSTTRG1_MASK              2
#define DC1CR_MODE_MASK                 4
#define DC1CR_INITLOG_MASK              8
#define DC1CR_PSTART_MASK               16
#define DC1CR_DCMEN_MASK                128
#define DC1CR_RSTTRG_MASK               3
#define DC1CR_RSTTRG_BITNUM             0


/*** DC1SCR1 - Data Codec 1 Status & Control Register 1; 0x00000021 ***/
typedef union {
  byte Byte;
  struct {
    byte             :1; 
    byte RISEFALL    :1;                                       /* RISE/FALL Selection bit */
    byte             :1; 
    byte ERRIEN      :1;                                       /* Error interrupt enable bit */
    byte _8OVF       :1;                                       /* 8 Bit Free running counter overflow flag */
    byte             :1; 
    byte CARRIER     :1;                                       /* Carrier flag */
    byte             :1; 
  } Bits;
} DC1SCR1STR;
extern volatile DC1SCR1STR _DC1SCR1 @0x00000021;
#define DC1SCR1                         _DC1SCR1.Byte
#define DC1SCR1_RISEFALL                _DC1SCR1.Bits.RISEFALL
#define DC1SCR1_ERRIEN                  _DC1SCR1.Bits.ERRIEN
#define DC1SCR1__8OVF                   _DC1SCR1.Bits._8OVF
#define DC1SCR1_CARRIER                 _DC1SCR1.Bits.CARRIER

#define DC1SCR1_RISEFALL_MASK           2
#define DC1SCR1_ERRIEN_MASK             8
#define DC1SCR1__8OVF_MASK              16
#define DC1SCR1_CARRIER_MASK            64


/*** DC1SR2 - Data Codec 1 Status Register 2; 0x00000022 ***/
typedef union {
  byte Byte;
  struct {
    byte CNT1DT      :1;                                       /* Comparator 1 match flag */
    byte CNT2DT      :1;                                       /* Comparator 2 match flag */
    byte CNT3DT      :1;                                       /* Comparator 3 match flag */
    byte CNT4DT      :1;                                       /* Comparator 4 match flag */
    byte RSTDT       :1;                                       /* 8 bit Free running counter Reset flag */
    byte             :1; 
    byte EDGE        :1;                                       /* Edge detection Flag */
    byte RISE        :1;                                       /* Rising Edge detection Flag */
  } Bits;
} DC1SR2STR;
extern volatile DC1SR2STR _DC1SR2 @0x00000022;
#define DC1SR2                          _DC1SR2.Byte
#define DC1SR2_CNT1DT                   _DC1SR2.Bits.CNT1DT
#define DC1SR2_CNT2DT                   _DC1SR2.Bits.CNT2DT
#define DC1SR2_CNT3DT                   _DC1SR2.Bits.CNT3DT
#define DC1SR2_CNT4DT                   _DC1SR2.Bits.CNT4DT
#define DC1SR2_RSTDT                    _DC1SR2.Bits.RSTDT
#define DC1SR2_EDGE                     _DC1SR2.Bits.EDGE
#define DC1SR2_RISE                     _DC1SR2.Bits.RISE

#define DC1SR2_CNT1DT_MASK              1
#define DC1SR2_CNT2DT_MASK              2
#define DC1SR2_CNT3DT_MASK              4
#define DC1SR2_CNT4DT_MASK              8
#define DC1SR2_RSTDT_MASK               16
#define DC1SR2_EDGE_MASK                64
#define DC1SR2_RISE_MASK                128


/*** DC1ICR - Data Codec 1 Interrupt Control Register; 0x00000023 ***/
typedef union {
  byte Byte;
  struct {
    byte CNT1IEN     :1;                                       /* CNT1DT Interrupt Enable bit */
    byte CNT2IEN     :1;                                       /* CNT2DT Interrupt Enable bit */
    byte CNT3IEN     :1;                                       /* CNT3DT Interrupt Enable bit */
    byte CNT4IEN     :1;                                       /* CNT4DT Interrupt Enable bit */
    byte RSTIEN      :1;                                       /* RSTDT Interrupt Enable bit */
    byte             :1; 
    byte EDGEIEN     :1;                                       /* EDGE Interrupt Enable bit */
    byte OVF_SEL     :1;                                       /* Counter overflow selection bit */
  } Bits;
} DC1ICRSTR;
extern volatile DC1ICRSTR _DC1ICR @0x00000023;
#define DC1ICR                          _DC1ICR.Byte
#define DC1ICR_CNT1IEN                  _DC1ICR.Bits.CNT1IEN
#define DC1ICR_CNT2IEN                  _DC1ICR.Bits.CNT2IEN
#define DC1ICR_CNT3IEN                  _DC1ICR.Bits.CNT3IEN
#define DC1ICR_CNT4IEN                  _DC1ICR.Bits.CNT4IEN
#define DC1ICR_RSTIEN                   _DC1ICR.Bits.RSTIEN
#define DC1ICR_EDGEIEN                  _DC1ICR.Bits.EDGEIEN
#define DC1ICR_OVF_SEL                  _DC1ICR.Bits.OVF_SEL

#define DC1ICR_CNT1IEN_MASK             1
#define DC1ICR_CNT2IEN_MASK             2
#define DC1ICR_CNT3IEN_MASK             4
#define DC1ICR_CNT4IEN_MASK             8
#define DC1ICR_RSTIEN_MASK              16
#define DC1ICR_EDGEIEN_MASK             64
#define DC1ICR_OVF_SEL_MASK             128


/*** DC1CNT - Data Codec 1 Counter Register; 0x00000024 ***/
typedef union {
  byte Byte;
  struct {
    byte CNT0        :1;                                       /* Data Codec 1 Counter Bit 0 */
    byte CNT1        :1;                                       /* Data Codec 1 Counter Bit 1 */
    byte CNT2        :1;                                       /* Data Codec 1 Counter Bit 2 */
    byte CNT3        :1;                                       /* Data Codec 1 Counter Bit 3 */