📄 mc68hc908jw32.h
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word Word;
/* Overlapped registers: */
struct {
/*** T1CH0H - TIM1 Channel 0 Register High; 0x00000011 ***/
union {
byte Byte;
} T1CH0HSTR;
#define T1CH0H _T1CH0.Overlap_STR.T1CH0HSTR.Byte
/*** T1CH0L - TIM1 Channel 0 Register Low; 0x00000012 ***/
union {
byte Byte;
} T1CH0LSTR;
#define T1CH0L _T1CH0.Overlap_STR.T1CH0LSTR.Byte
} Overlap_STR;
} T1CH0STR;
extern volatile T1CH0STR _T1CH0 @0x00000011;
#define T1CH0 _T1CH0.Word
/* T1CH_ARR: Access 2 T1CHx registers in an array */
#define T1CH_ARR ((word *) &T1CH0)
/*** T1SC1 - TIM1 Channel 1 Status and Control Register; 0x00000013 ***/
typedef union {
byte Byte;
struct {
byte CH1MAX :1; /* Channel 1 Maximum Duty Cycle Bit */
byte TOV1 :1; /* Toggle-On-Overflow Bit */
byte ELS1A :1; /* Edge/Level Select Bit A */
byte ELS1B :1; /* Edge/Level Select Bit B */
byte MS1A :1; /* Mode Select Bit A */
byte :1;
byte CH1IE :1; /* Channel 1 Interrupt Enable Bit */
byte CH1F :1; /* Channel 1 Flag Bit */
} Bits;
struct {
byte :1;
byte grpTOV_1 :1;
byte grpELS1x :2;
byte grpMS1x :1;
byte :1;
byte :1;
byte :1;
} MergedBits;
} T1SC1STR;
extern volatile T1SC1STR _T1SC1 @0x00000013;
#define T1SC1 _T1SC1.Byte
#define T1SC1_CH1MAX _T1SC1.Bits.CH1MAX
#define T1SC1_TOV1 _T1SC1.Bits.TOV1
#define T1SC1_ELS1A _T1SC1.Bits.ELS1A
#define T1SC1_ELS1B _T1SC1.Bits.ELS1B
#define T1SC1_MS1A _T1SC1.Bits.MS1A
#define T1SC1_CH1IE _T1SC1.Bits.CH1IE
#define T1SC1_CH1F _T1SC1.Bits.CH1F
#define T1SC1_ELS1x _T1SC1.MergedBits.grpELS1x
#define T1SC1_CH1MAX_MASK 1
#define T1SC1_TOV1_MASK 2
#define T1SC1_ELS1A_MASK 4
#define T1SC1_ELS1B_MASK 8
#define T1SC1_MS1A_MASK 16
#define T1SC1_CH1IE_MASK 64
#define T1SC1_CH1F_MASK 128
#define T1SC1_ELS1x_MASK 12
#define T1SC1_ELS1x_BITNUM 2
/*** T1CH1 - TIM1 Channel 1 Register; 0x00000014 ***/
typedef union {
word Word;
/* Overlapped registers: */
struct {
/*** T1CH1H - TIM1 Channel 1 Register High; 0x00000014 ***/
union {
byte Byte;
} T1CH1HSTR;
#define T1CH1H _T1CH1.Overlap_STR.T1CH1HSTR.Byte
/*** T1CH1L - TIM1 Channel 1 Register Low; 0x00000015 ***/
union {
byte Byte;
} T1CH1LSTR;
#define T1CH1L _T1CH1.Overlap_STR.T1CH1LSTR.Byte
} Overlap_STR;
} T1CH1STR;
extern volatile T1CH1STR _T1CH1 @0x00000014;
#define T1CH1 _T1CH1.Word
/*** KBSCR - Keyboard Status and Control Register; 0x00000016 ***/
typedef union {
byte Byte;
struct {
byte MODEK :1; /* Keyboard Triggering Sensitivity Bit */
byte IMASKK :1; /* Keyboard Interrupt Mask Bit */
byte ACKK :1; /* Keyboard Acknowledge Bit */
byte KEYF :1; /* Keyboard Flag Bit */
byte :1;
byte :1;
byte :1;
byte :1;
} Bits;
} KBSCRSTR;
extern volatile KBSCRSTR _KBSCR @0x00000016;
#define KBSCR _KBSCR.Byte
#define KBSCR_MODEK _KBSCR.Bits.MODEK
#define KBSCR_IMASKK _KBSCR.Bits.IMASKK
#define KBSCR_ACKK _KBSCR.Bits.ACKK
#define KBSCR_KEYF _KBSCR.Bits.KEYF
#define KBSCR_MODEK_MASK 1
#define KBSCR_IMASKK_MASK 2
#define KBSCR_ACKK_MASK 4
#define KBSCR_KEYF_MASK 8
/*** KBIER - Keyboard Interrrupt Enable Register KBIER; 0x00000017 ***/
typedef union {
byte Byte;
struct {
byte KBIE0 :1; /* Keyboard Interrupt Enable Bit 0 */
byte KBIE1 :1; /* Keyboard Interrupt Enable Bit 1 */
byte KBIE2 :1; /* Keyboard Interrupt Enable Bit 2 */
byte KBIE3 :1; /* Keyboard Interrupt Enable Bit 3 */
byte KBIE4 :1; /* Keyboard Interrupt Enable Bit 4 */
byte KBIE5 :1; /* Keyboard Interrupt Enable Bit 5 */
byte KBIE6 :1; /* Keyboard Interrupt Enable Bit 6 */
byte KBIE7 :1; /* Keyboard Interrupt Enable Bit 7 */
} Bits;
} KBIERSTR;
extern volatile KBIERSTR _KBIER @0x00000017;
#define KBIER _KBIER.Byte
#define KBIER_KBIE0 _KBIER.Bits.KBIE0
#define KBIER_KBIE1 _KBIER.Bits.KBIE1
#define KBIER_KBIE2 _KBIER.Bits.KBIE2
#define KBIER_KBIE3 _KBIER.Bits.KBIE3
#define KBIER_KBIE4 _KBIER.Bits.KBIE4
#define KBIER_KBIE5 _KBIER.Bits.KBIE5
#define KBIER_KBIE6 _KBIER.Bits.KBIE6
#define KBIER_KBIE7 _KBIER.Bits.KBIE7
#define KBIER_KBIE0_MASK 1
#define KBIER_KBIE1_MASK 2
#define KBIER_KBIE2_MASK 4
#define KBIER_KBIE3_MASK 8
#define KBIER_KBIE4_MASK 16
#define KBIER_KBIE5_MASK 32
#define KBIER_KBIE6_MASK 64
#define KBIER_KBIE7_MASK 128
/*** TBCR - Timebase Control Register; 0x00000018 ***/
typedef union {
byte Byte;
struct {
byte :1;
byte TBON :1; /* Timebase Enabled */
byte TBIE :1; /* Timebase Interrupt Enable */
byte TACK :1; /* Timebase ACKnowledge */
byte TBR0 :1; /* Timebase Rate Selection Bit 0 */
byte TBR1 :1; /* Timebase Rate Selection Bit 1 */
byte TBR2 :1; /* Timebase Rate Selection Bit 2 */
byte TBIF :1; /* Timebase Interrupt Flag */
} Bits;
struct {
byte :1;
byte :1;
byte :1;
byte :1;
byte grpTBR :3;
byte :1;
} MergedBits;
} TBCRSTR;
extern volatile TBCRSTR _TBCR @0x00000018;
#define TBCR _TBCR.Byte
#define TBCR_TBON _TBCR.Bits.TBON
#define TBCR_TBIE _TBCR.Bits.TBIE
#define TBCR_TACK _TBCR.Bits.TACK
#define TBCR_TBR0 _TBCR.Bits.TBR0
#define TBCR_TBR1 _TBCR.Bits.TBR1
#define TBCR_TBR2 _TBCR.Bits.TBR2
#define TBCR_TBIF _TBCR.Bits.TBIF
#define TBCR_TBR _TBCR.MergedBits.grpTBR
#define TBCR_TBON_MASK 2
#define TBCR_TBIE_MASK 4
#define TBCR_TACK_MASK 8
#define TBCR_TBR0_MASK 16
#define TBCR_TBR1_MASK 32
#define TBCR_TBR2_MASK 64
#define TBCR_TBIF_MASK 128
#define TBCR_TBR_MASK 112
#define TBCR_TBR_BITNUM 4
/*** PS2CSR - I/O Control Register ; 0x00000019 ***/
typedef union {
byte Byte;
struct {
byte PS2EN :1; /* PS2 Clock Generator Module Enable */
byte CLKEN :1; /* Clock Output Enable bit */
byte PS2IEN :1; /* PS2 Interrupt Mask */
byte CSEL0 :1; /* Clock Frequency Selection bit 0 */
byte CSEL1 :1; /* Clock Frequency Selection bit 1 */
byte PRE :1; /* Prescalar Selection */
byte PS2IF :1; /* PS2 Interrupt Flag */
byte PSTATUS :1; /* Port Status Flag */
} Bits;
struct {
byte :1;
byte :1;
byte :1;
byte grpCSEL :2;
byte :1;
byte :1;
byte :1;
} MergedBits;
} PS2CSRSTR;
extern volatile PS2CSRSTR _PS2CSR @0x00000019;
#define PS2CSR _PS2CSR.Byte
#define PS2CSR_PS2EN _PS2CSR.Bits.PS2EN
#define PS2CSR_CLKEN _PS2CSR.Bits.CLKEN
#define PS2CSR_PS2IEN _PS2CSR.Bits.PS2IEN
#define PS2CSR_CSEL0 _PS2CSR.Bits.CSEL0
#define PS2CSR_CSEL1 _PS2CSR.Bits.CSEL1
#define PS2CSR_PRE _PS2CSR.Bits.PRE
#define PS2CSR_PS2IF _PS2CSR.Bits.PS2IF
#define PS2CSR_PSTATUS _PS2CSR.Bits.PSTATUS
#define PS2CSR_CSEL _PS2CSR.MergedBits.grpCSEL
#define PS2CSR_PS2EN_MASK 1
#define PS2CSR_CLKEN_MASK 2
#define PS2CSR_PS2IEN_MASK 4
#define PS2CSR_CSEL0_MASK 8
#define PS2CSR_CSEL1_MASK 16
#define PS2CSR_PRE_MASK 32
#define PS2CSR_PS2IF_MASK 64
#define PS2CSR_PSTATUS_MASK 128
#define PS2CSR_CSEL_MASK 24
#define PS2CSR_CSEL_BITNUM 3
/*** POCR1 - Port Option Control Register 1; 0x0000001A ***/
typedef union {
byte Byte;
struct {
byte LEDB0 :1; /* Port B LED Drive Enable Bit 0 */
byte LEDB1 :1; /* Port B LED Drive Enable Bit 1 */
byte LEDB2 :1; /* Port B LED Drive Enable Bit 2 */
byte LEDB3 :1; /* Port B LED Drive Enable Bit 3 */
byte LEDB4 :1; /* Port B LED Drive Enable Bit 4 */
byte LEDB5 :1; /* Port B LED Drive Enable Bit 5 */
byte LEDB6 :1; /* Port B LED Drive Enable Bit 6 */
byte LEDB7 :1; /* Port B LED Drive Enable Bit 7 */
} Bits;
} POCR1STR;
extern volatile POCR1STR _POCR1 @0x0000001A;
#define POCR1 _POCR1.Byte
#define POCR1_LEDB0 _POCR1.Bits.LEDB0
#define POCR1_LEDB1 _POCR1.Bits.LEDB1
#define POCR1_LEDB2 _POCR1.Bits.LEDB2
#define POCR1_LEDB3 _POCR1.Bits.LEDB3
#define POCR1_LEDB4 _POCR1.Bits.LEDB4
#define POCR1_LEDB5 _POCR1.Bits.LEDB5
#define POCR1_LEDB6 _POCR1.Bits.LEDB6
#define POCR1_LEDB7 _POCR1.Bits.LEDB7
#define POCR1_LEDB0_MASK 1
#define POCR1_LEDB1_MASK 2
#define POCR1_LEDB2_MASK 4
#define POCR1_LEDB3_MASK 8
#define POCR1_LEDB4_MASK 16
#define POCR1_LEDB5_MASK 32
#define POCR1_LEDB6_MASK 64
#define POCR1_LEDB7_MASK 128
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