📄 mc68hc908jw32.h
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struct {
byte grpDDRC :4;
byte :1;
byte :1;
byte :1;
byte :1;
} MergedBits;
} DDRCSTR;
extern volatile DDRCSTR _DDRC @0x00000006;
#define DDRC _DDRC.Byte
#define DDRC_DDRC0 _DDRC.Bits.DDRC0
#define DDRC_DDRC1 _DDRC.Bits.DDRC1
#define DDRC_DDRC2 _DDRC.Bits.DDRC2
#define DDRC_DDRC3 _DDRC.Bits.DDRC3
#define DDRC_DDRC _DDRC.MergedBits.grpDDRC
#define DDRC_DDRC0_MASK 1
#define DDRC_DDRC1_MASK 2
#define DDRC_DDRC2_MASK 4
#define DDRC_DDRC3_MASK 8
#define DDRC_DDRC_MASK 15
#define DDRC_DDRC_BITNUM 0
/*** DDRD - Data Direction Register D; 0x00000007 ***/
typedef union {
byte Byte;
struct {
byte DDRD0 :1; /* Data Direction Register D Bit 0 */
byte DDRD1 :1; /* Data Direction Register D Bit 1 */
byte DDRD2 :1; /* Data Direction Register D Bit 2 */
byte DDRD3 :1; /* Data Direction Register D Bit 3 */
byte DDRD4 :1; /* Data Direction Register D Bit 4 */
byte DDRD5 :1; /* Data Direction Register D Bit 5 */
byte DDRD6 :1; /* Data Direction Register D Bit 6 */
byte DDRD7 :1; /* Data Direction Register D Bit 7 */
} Bits;
} DDRDSTR;
extern volatile DDRDSTR _DDRD @0x00000007;
#define DDRD _DDRD.Byte
#define DDRD_DDRD0 _DDRD.Bits.DDRD0
#define DDRD_DDRD1 _DDRD.Bits.DDRD1
#define DDRD_DDRD2 _DDRD.Bits.DDRD2
#define DDRD_DDRD3 _DDRD.Bits.DDRD3
#define DDRD_DDRD4 _DDRD.Bits.DDRD4
#define DDRD_DDRD5 _DDRD.Bits.DDRD5
#define DDRD_DDRD6 _DDRD.Bits.DDRD6
#define DDRD_DDRD7 _DDRD.Bits.DDRD7
#define DDRD_DDRD0_MASK 1
#define DDRD_DDRD1_MASK 2
#define DDRD_DDRD2_MASK 4
#define DDRD_DDRD3_MASK 8
#define DDRD_DDRD4_MASK 16
#define DDRD_DDRD5_MASK 32
#define DDRD_DDRD6_MASK 64
#define DDRD_DDRD7_MASK 128
/*** PTE - Port E Data Register; 0x00000008 ***/
typedef union {
byte Byte;
struct {
byte :1;
byte :1;
byte PTE2 :1; /* Port E Data Bit 2 */
byte PTE3 :1; /* Port E Data Bit 3 */
byte PTE4 :1; /* Port E Data Bit 4 */
byte PTE5 :1; /* Port E Data Bit 5 */
byte PTE6 :1; /* Port E Data Bit 6 */
byte PTE7 :1; /* Port E Data Bit 7 */
} Bits;
struct {
byte :1;
byte :1;
byte grpPTE_2 :6;
} MergedBits;
} PTESTR;
extern volatile PTESTR _PTE @0x00000008;
#define PTE _PTE.Byte
#define PTE_PTE2 _PTE.Bits.PTE2
#define PTE_PTE3 _PTE.Bits.PTE3
#define PTE_PTE4 _PTE.Bits.PTE4
#define PTE_PTE5 _PTE.Bits.PTE5
#define PTE_PTE6 _PTE.Bits.PTE6
#define PTE_PTE7 _PTE.Bits.PTE7
#define PTE_PTE_2 _PTE.MergedBits.grpPTE_2
#define PTE_PTE2_MASK 4
#define PTE_PTE3_MASK 8
#define PTE_PTE4_MASK 16
#define PTE_PTE5_MASK 32
#define PTE_PTE6_MASK 64
#define PTE_PTE7_MASK 128
#define PTE_PTE_2_MASK 252
#define PTE_PTE_2_BITNUM 2
/*** DDRE - Data Direction Register E; 0x00000009 ***/
typedef union {
byte Byte;
struct {
byte :1;
byte :1;
byte DDRE2 :1; /* Data Direction Register E Bit 2 */
byte DDRE3 :1; /* Data Direction Register E Bit 3 */
byte DDRE4 :1; /* Data Direction Register E Bit 4 */
byte DDRE5 :1; /* Data Direction Register E Bit 5 */
byte DDRE6 :1; /* Data Direction Register E Bit 6 */
byte DDRE7 :1; /* Data Direction Register E Bit 7 */
} Bits;
struct {
byte :1;
byte :1;
byte grpDDRE_2 :6;
} MergedBits;
} DDRESTR;
extern volatile DDRESTR _DDRE @0x00000009;
#define DDRE _DDRE.Byte
#define DDRE_DDRE2 _DDRE.Bits.DDRE2
#define DDRE_DDRE3 _DDRE.Bits.DDRE3
#define DDRE_DDRE4 _DDRE.Bits.DDRE4
#define DDRE_DDRE5 _DDRE.Bits.DDRE5
#define DDRE_DDRE6 _DDRE.Bits.DDRE6
#define DDRE_DDRE7 _DDRE.Bits.DDRE7
#define DDRE_DDRE_2 _DDRE.MergedBits.grpDDRE_2
#define DDRE_DDRE2_MASK 4
#define DDRE_DDRE3_MASK 8
#define DDRE_DDRE4_MASK 16
#define DDRE_DDRE5_MASK 32
#define DDRE_DDRE6_MASK 64
#define DDRE_DDRE7_MASK 128
#define DDRE_DDRE_2_MASK 252
#define DDRE_DDRE_2_BITNUM 2
/*** T1SC - TIM1 Status and Control Register TSC; 0x0000000A ***/
typedef union {
byte Byte;
struct {
byte PS0 :1; /* Prescaler Select Bit */
byte PS1 :1; /* Prescaler Select Bit 1 */
byte PS2 :1; /* Prescaler Select Bit 2 */
byte :1;
byte TRST :1; /* TIM1 Reset Bit */
byte TSTOP :1; /* TIM1 Stop Bit */
byte TOIE :1; /* TIM1 Overflow Interrupt Enable Bit */
byte TOF :1; /* TIM1 Overflow Flag Bit */
} Bits;
struct {
byte grpPS :3;
byte :1;
byte :1;
byte :1;
byte :1;
byte :1;
} MergedBits;
} T1SCSTR;
extern volatile T1SCSTR _T1SC @0x0000000A;
#define T1SC _T1SC.Byte
#define T1SC_PS0 _T1SC.Bits.PS0
#define T1SC_PS1 _T1SC.Bits.PS1
#define T1SC_PS2 _T1SC.Bits.PS2
#define T1SC_TRST _T1SC.Bits.TRST
#define T1SC_TSTOP _T1SC.Bits.TSTOP
#define T1SC_TOIE _T1SC.Bits.TOIE
#define T1SC_TOF _T1SC.Bits.TOF
#define T1SC_PS _T1SC.MergedBits.grpPS
#define T1SC_PS0_MASK 1
#define T1SC_PS1_MASK 2
#define T1SC_PS2_MASK 4
#define T1SC_TRST_MASK 16
#define T1SC_TSTOP_MASK 32
#define T1SC_TOIE_MASK 64
#define T1SC_TOF_MASK 128
#define T1SC_PS_MASK 7
#define T1SC_PS_BITNUM 0
/*** T1CNT - TIM1 Counter Register; 0x0000000C ***/
typedef union {
word Word;
/* Overlapped registers: */
struct {
/*** T1CNTH - TIM1 Counter Register High; 0x0000000C ***/
union {
byte Byte;
} T1CNTHSTR;
#define T1CNTH _T1CNT.Overlap_STR.T1CNTHSTR.Byte
/*** T1CNTL - TIM1 Counter Register Low; 0x0000000D ***/
union {
byte Byte;
} T1CNTLSTR;
#define T1CNTL _T1CNT.Overlap_STR.T1CNTLSTR.Byte
} Overlap_STR;
} T1CNTSTR;
extern volatile T1CNTSTR _T1CNT @0x0000000C;
#define T1CNT _T1CNT.Word
/*** T1MOD - TIM1 Counter Modulo Register; 0x0000000E ***/
typedef union {
word Word;
/* Overlapped registers: */
struct {
/*** T1MODH - TIM1 Counter Modulo Register High; 0x0000000E ***/
union {
byte Byte;
} T1MODHSTR;
#define T1MODH _T1MOD.Overlap_STR.T1MODHSTR.Byte
/*** T1MODL - TIM1 Counter Modulo Register Low; 0x0000000F ***/
union {
byte Byte;
} T1MODLSTR;
#define T1MODL _T1MOD.Overlap_STR.T1MODLSTR.Byte
} Overlap_STR;
} T1MODSTR;
extern volatile T1MODSTR _T1MOD @0x0000000E;
#define T1MOD _T1MOD.Word
/*** T1SC0 - TIM1 Channel 0 Status and Control Register; 0x00000010 ***/
typedef union {
byte Byte;
struct {
byte CH0MAX :1; /* Channel 0 Maximum Duty Cycle Bit */
byte TOV0 :1; /* Toggle-On-Overflow Bit */
byte ELS0A :1; /* Edge/Level Select Bit A */
byte ELS0B :1; /* Edge/Level Select Bit B */
byte MS0A :1; /* Mode Select Bit A */
byte MS0B :1; /* Mode Select Bit B */
byte CH0IE :1; /* Channel 0 Interrupt Enable Bit */
byte CH0F :1; /* Channel 0 Flag Bit */
} Bits;
struct {
byte :1;
byte grpTOV :1;
byte grpELS0x :2;
byte grpMS0x :2;
byte :1;
byte :1;
} MergedBits;
} T1SC0STR;
extern volatile T1SC0STR _T1SC0 @0x00000010;
#define T1SC0 _T1SC0.Byte
#define T1SC0_CH0MAX _T1SC0.Bits.CH0MAX
#define T1SC0_TOV0 _T1SC0.Bits.TOV0
#define T1SC0_ELS0A _T1SC0.Bits.ELS0A
#define T1SC0_ELS0B _T1SC0.Bits.ELS0B
#define T1SC0_MS0A _T1SC0.Bits.MS0A
#define T1SC0_MS0B _T1SC0.Bits.MS0B
#define T1SC0_CH0IE _T1SC0.Bits.CH0IE
#define T1SC0_CH0F _T1SC0.Bits.CH0F
#define T1SC0_ELS0x _T1SC0.MergedBits.grpELS0x
#define T1SC0_MS0x _T1SC0.MergedBits.grpMS0x
#define T1SC0_CH0MAX_MASK 1
#define T1SC0_TOV0_MASK 2
#define T1SC0_ELS0A_MASK 4
#define T1SC0_ELS0B_MASK 8
#define T1SC0_MS0A_MASK 16
#define T1SC0_MS0B_MASK 32
#define T1SC0_CH0IE_MASK 64
#define T1SC0_CH0F_MASK 128
#define T1SC0_ELS0x_MASK 12
#define T1SC0_ELS0x_BITNUM 2
#define T1SC0_MS0x_MASK 48
#define T1SC0_MS0x_BITNUM 4
/*** T1CH0 - TIM1 Channel 0 Register; 0x00000011 ***/
typedef union {
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