📄 mc68hc908jw32.h
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/* Based on CPU DB MC68HC908JW32_52, version 2.87.004 (RegistersPrg V1.103) */
/*
** ###################################################################
** Filename : MC68HC908JW32.h
** Processor : MC68HC908JW32FB
** FileFormat: V1.103
** DataSheet : 68HC908JW32 Rev. 1.0 10/2004
** Compiler : Metrowerks C compiler
** Date/Time : 07.03.2005, 16:46
** Abstract :
** This header implements the mapping of IO devices.
**
** (c) Copyright UNIS, spol. s r.o. 1997-2003
** UNIS, spol. s r.o.
** Jundrovska 33
** 624 00 Brno
** Czech Republic
** http : www.processorexpert.com
** mail : info@processorexpert.com
** ###################################################################
*/
#ifndef _MC68HC908JW32_H
#define _MC68HC908JW32_H
/* Types definition */
typedef unsigned char byte;
typedef unsigned int word;
typedef unsigned long dword;
typedef unsigned long dlong[2];
#ifndef __RESET_WATCHDOG_MACRO
#define __RESET_WATCHDOG_MACRO
/* Watchdog reset macro */
#ifdef _lint
#define __RESET_WATCHDOG() /* empty */
#else
#define __RESET_WATCHDOG() {asm sta COPCTL;} /* Just write a byte to feed the dog */
#endif
#endif /* __RESET_WATCHDOG_MACRO */
#define REG_BASE 0x0000 /* Base address for the I/O register block */
#pragma MESSAGE DISABLE C1106 /* WARNING C1106: Non-standard bitfield type */
/**************** interrupt vector table ****************/
#define INT_TBM 0x0000FFDE
#define INT_KBI 0x0000FFE0
#define INT_SPITransmit 0x0000FFE2
#define INT_SPIReceive 0x0000FFE4
#define INT_DCM2Receive 0x0000FFE6
#define INT_DCM1Transmit 0x0000FFE8
#define INT_DCM1Receive 0x0000FFEA
#define INT_PS2 0x0000FFEC
#define INT_TIM1Ovr 0x0000FFEE
#define INT_TIM1CH1 0x0000FFF0
#define INT_TIM1CH0 0x0000FFF2
#define INT_PLL 0x0000FFF4
#define INT_IRQ 0x0000FFF6
#define INT_USBEndpoint 0x0000FFF8
#define INT_USBSystem 0x0000FFFA
#define INT_SWI 0x0000FFFC
#define INT_RESET 0x0000FFFE
/**************** registers I/O map ****************/
/*** PTA - Port A Data Register; 0x00000000 ***/
typedef union {
byte Byte;
struct {
byte PTA0 :1; /* Port A Data Bit 0 */
byte PTA1 :1; /* Port A Data Bit 1 */
byte PTA2 :1; /* Port A Data Bit 2 */
byte PTA3 :1; /* Port A Data Bit 3 */
byte PTA4 :1; /* Port A Data Bit 4 */
byte PTA5 :1; /* Port A Data Bit 5 */
byte PTA6 :1; /* Port A Data Bit 6 */
byte PTA7 :1; /* Port A Data Bit 7 */
} Bits;
} PTASTR;
extern volatile PTASTR _PTA @0x00000000;
#define PTA _PTA.Byte
#define PTA_PTA0 _PTA.Bits.PTA0
#define PTA_PTA1 _PTA.Bits.PTA1
#define PTA_PTA2 _PTA.Bits.PTA2
#define PTA_PTA3 _PTA.Bits.PTA3
#define PTA_PTA4 _PTA.Bits.PTA4
#define PTA_PTA5 _PTA.Bits.PTA5
#define PTA_PTA6 _PTA.Bits.PTA6
#define PTA_PTA7 _PTA.Bits.PTA7
#define PTA_PTA0_MASK 1
#define PTA_PTA1_MASK 2
#define PTA_PTA2_MASK 4
#define PTA_PTA3_MASK 8
#define PTA_PTA4_MASK 16
#define PTA_PTA5_MASK 32
#define PTA_PTA6_MASK 64
#define PTA_PTA7_MASK 128
/*** PTB - Port B Data Register; 0x00000001 ***/
typedef union {
byte Byte;
struct {
byte PTB0 :1; /* Port B Data Bit 0 */
byte PTB1 :1; /* Port B Data Bit 1 */
byte PTB2 :1; /* Port B Data Bit 2 */
byte PTB3 :1; /* Port B Data Bit 3 */
byte PTB4 :1; /* Port B Data Bit 4 */
byte PTB5 :1; /* Port B Data Bit 5 */
byte PTB6 :1; /* Port B Data Bit 6 */
byte PTB7 :1; /* Port B Data Bit 7 */
} Bits;
} PTBSTR;
extern volatile PTBSTR _PTB @0x00000001;
#define PTB _PTB.Byte
#define PTB_PTB0 _PTB.Bits.PTB0
#define PTB_PTB1 _PTB.Bits.PTB1
#define PTB_PTB2 _PTB.Bits.PTB2
#define PTB_PTB3 _PTB.Bits.PTB3
#define PTB_PTB4 _PTB.Bits.PTB4
#define PTB_PTB5 _PTB.Bits.PTB5
#define PTB_PTB6 _PTB.Bits.PTB6
#define PTB_PTB7 _PTB.Bits.PTB7
#define PTB_PTB0_MASK 1
#define PTB_PTB1_MASK 2
#define PTB_PTB2_MASK 4
#define PTB_PTB3_MASK 8
#define PTB_PTB4_MASK 16
#define PTB_PTB5_MASK 32
#define PTB_PTB6_MASK 64
#define PTB_PTB7_MASK 128
/*** PTC - Port C Data Register; 0x00000002 ***/
typedef union {
byte Byte;
struct {
byte PTC0 :1; /* Port C Data Bit 0 */
byte PTC1 :1; /* Port C Data Bit 1 */
byte PTC2 :1; /* Port C Data Bit 2 */
byte PTC3 :1; /* Port C Data Bit 3 */
byte :1;
byte :1;
byte :1;
byte :1;
} Bits;
struct {
byte grpPTC :4;
byte :1;
byte :1;
byte :1;
byte :1;
} MergedBits;
} PTCSTR;
extern volatile PTCSTR _PTC @0x00000002;
#define PTC _PTC.Byte
#define PTC_PTC0 _PTC.Bits.PTC0
#define PTC_PTC1 _PTC.Bits.PTC1
#define PTC_PTC2 _PTC.Bits.PTC2
#define PTC_PTC3 _PTC.Bits.PTC3
#define PTC_PTC _PTC.MergedBits.grpPTC
#define PTC_PTC0_MASK 1
#define PTC_PTC1_MASK 2
#define PTC_PTC2_MASK 4
#define PTC_PTC3_MASK 8
#define PTC_PTC_MASK 15
#define PTC_PTC_BITNUM 0
/*** PTD - Port D Data Register; 0x00000003 ***/
typedef union {
byte Byte;
struct {
byte PTD0 :1; /* Port D Data Bit 0 */
byte PTD1 :1; /* Port D Data Bit 1 */
byte PTD2 :1; /* Port D Data Bit 2 */
byte PTD3 :1; /* Port D Data Bit 3 */
byte PTD4 :1; /* Port D Data Bit 4 */
byte PTD5 :1; /* Port D Data Bit 5 */
byte PTD6 :1; /* Port D Data Bit 6 */
byte PTD7 :1; /* Port D Data Bit 7 */
} Bits;
} PTDSTR;
extern volatile PTDSTR _PTD @0x00000003;
#define PTD _PTD.Byte
#define PTD_PTD0 _PTD.Bits.PTD0
#define PTD_PTD1 _PTD.Bits.PTD1
#define PTD_PTD2 _PTD.Bits.PTD2
#define PTD_PTD3 _PTD.Bits.PTD3
#define PTD_PTD4 _PTD.Bits.PTD4
#define PTD_PTD5 _PTD.Bits.PTD5
#define PTD_PTD6 _PTD.Bits.PTD6
#define PTD_PTD7 _PTD.Bits.PTD7
#define PTD_PTD0_MASK 1
#define PTD_PTD1_MASK 2
#define PTD_PTD2_MASK 4
#define PTD_PTD3_MASK 8
#define PTD_PTD4_MASK 16
#define PTD_PTD5_MASK 32
#define PTD_PTD6_MASK 64
#define PTD_PTD7_MASK 128
/*** DDRA - Data Direction Register A; 0x00000004 ***/
typedef union {
byte Byte;
struct {
byte DDRA0 :1; /* Data Direction Register A Bit 0 */
byte DDRA1 :1; /* Data Direction Register A Bit 1 */
byte DDRA2 :1; /* Data Direction Register A Bit 2 */
byte DDRA3 :1; /* Data Direction Register A Bit 3 */
byte DDRA4 :1; /* Data Direction Register A Bit 4 */
byte DDRA5 :1; /* Data Direction Register A Bit 5 */
byte DDRA6 :1; /* Data Direction Register A Bit 6 */
byte DDRA7 :1; /* Data Direction Register A Bit 7 */
} Bits;
} DDRASTR;
extern volatile DDRASTR _DDRA @0x00000004;
#define DDRA _DDRA.Byte
#define DDRA_DDRA0 _DDRA.Bits.DDRA0
#define DDRA_DDRA1 _DDRA.Bits.DDRA1
#define DDRA_DDRA2 _DDRA.Bits.DDRA2
#define DDRA_DDRA3 _DDRA.Bits.DDRA3
#define DDRA_DDRA4 _DDRA.Bits.DDRA4
#define DDRA_DDRA5 _DDRA.Bits.DDRA5
#define DDRA_DDRA6 _DDRA.Bits.DDRA6
#define DDRA_DDRA7 _DDRA.Bits.DDRA7
#define DDRA_DDRA0_MASK 1
#define DDRA_DDRA1_MASK 2
#define DDRA_DDRA2_MASK 4
#define DDRA_DDRA3_MASK 8
#define DDRA_DDRA4_MASK 16
#define DDRA_DDRA5_MASK 32
#define DDRA_DDRA6_MASK 64
#define DDRA_DDRA7_MASK 128
/*** DDRB - Data Direction Register B; 0x00000005 ***/
typedef union {
byte Byte;
struct {
byte DDRB0 :1; /* Data Direction Register B Bit 0 */
byte DDRB1 :1; /* Data Direction Register B Bit 1 */
byte DDRB2 :1; /* Data Direction Register B Bit 2 */
byte DDRB3 :1; /* Data Direction Register B Bit 3 */
byte DDRB4 :1; /* Data Direction Register B Bit 4 */
byte DDRB5 :1; /* Data Direction Register B Bit 5 */
byte DDRB6 :1; /* Data Direction Register B Bit 6 */
byte DDRB7 :1; /* Data Direction Register B Bit 7 */
} Bits;
} DDRBSTR;
extern volatile DDRBSTR _DDRB @0x00000005;
#define DDRB _DDRB.Byte
#define DDRB_DDRB0 _DDRB.Bits.DDRB0
#define DDRB_DDRB1 _DDRB.Bits.DDRB1
#define DDRB_DDRB2 _DDRB.Bits.DDRB2
#define DDRB_DDRB3 _DDRB.Bits.DDRB3
#define DDRB_DDRB4 _DDRB.Bits.DDRB4
#define DDRB_DDRB5 _DDRB.Bits.DDRB5
#define DDRB_DDRB6 _DDRB.Bits.DDRB6
#define DDRB_DDRB7 _DDRB.Bits.DDRB7
#define DDRB_DDRB0_MASK 1
#define DDRB_DDRB1_MASK 2
#define DDRB_DDRB2_MASK 4
#define DDRB_DDRB3_MASK 8
#define DDRB_DDRB4_MASK 16
#define DDRB_DDRB5_MASK 32
#define DDRB_DDRB6_MASK 64
#define DDRB_DDRB7_MASK 128
/*** DDRC - Data Direction Register C; 0x00000006 ***/
typedef union {
byte Byte;
struct {
byte DDRC0 :1; /* Data Direction Register C Bit 0 */
byte DDRC1 :1; /* Data Direction Register C Bit 1 */
byte DDRC2 :1; /* Data Direction Register C Bit 2 */
byte DDRC3 :1; /* Data Direction Register C Bit 3 */
byte :1;
byte :1;
byte :1;
byte :1;
} Bits;
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