system.h

使用61505控制其的LCD的驱动程序

/* system.h
 *
 * Machine generated for a CPU named "cpu_0" as defined in:
 * d:\altera\T\software\lcddrive_syslib\..\..\CPU.ptf
 *
 * Generated: 2008-07-27 19:04:42.89
 *
 */

#ifndef __SYSTEM_H_
#define __SYSTEM_H_

/*

DO NOT MODIFY THIS FILE

   Changing this file will have subtle consequences
   which will almost certainly lead to a nonfunctioning
   system. If you do modify this file, be aware that your
   changes will be overwritten and lost when this file
   is generated again.

DO NOT MODIFY THIS FILE

*/

/******************************************************************************
*                                                                             *
* License Agreement                                                           *
*                                                                             *
* Copyright (c) 2003 Altera Corporation, San Jose, California, USA.           *
* All rights reserved.                                                        *
*                                                                             *
* Permission is hereby granted, free of charge, to any person obtaining a     *
* copy of this software and associated documentation files (the "Software"),  *
* to deal in the Software without restriction, including without limitation   *
* the rights to use, copy, modify, merge, publish, distribute, sublicense,    *
* and/or sell copies of the Software, and to permit persons to whom the       *
* Software is furnished to do so, subject to the following conditions:        *
*                                                                             *
* The above copyright notice and this permission notice shall be included in  *
* all copies or substantial portions of the Software.                         *
*                                                                             *
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR  *
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,    *
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE *
* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER      *
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING     *
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER         *
* DEALINGS IN THE SOFTWARE.                                                   *
*                                                                             *
* This agreement shall be governed in all respects by the laws of the State   *
* of California and by the laws of the United States of America.              *
*                                                                             *
******************************************************************************/

/*
 * system configuration
 *
 */

#define ALT_SYSTEM_NAME "CPU"
#define ALT_CPU_NAME "cpu_0"
#define ALT_CPU_ARCHITECTURE "altera_nios2"
#define ALT_DEVICE_FAMILY "CYCLONE"
#define ALT_STDIN "/dev/jtag_uart_0"
#define ALT_STDIN_TYPE "altera_avalon_jtag_uart"
#define ALT_STDIN_BASE 0x00808910
#define ALT_STDIN_DEV jtag_uart_0
#define ALT_STDIN_PRESENT
#define ALT_STDOUT "/dev/jtag_uart_0"
#define ALT_STDOUT_TYPE "altera_avalon_jtag_uart"
#define ALT_STDOUT_BASE 0x00808910
#define ALT_STDOUT_DEV jtag_uart_0
#define ALT_STDOUT_PRESENT
#define ALT_STDERR "/dev/jtag_uart_0"
#define ALT_STDERR_TYPE "altera_avalon_jtag_uart"
#define ALT_STDERR_BASE 0x00808910
#define ALT_STDERR_DEV jtag_uart_0
#define ALT_STDERR_PRESENT
#define ALT_CPU_FREQ 100000000
#define ALT_IRQ_BASE NULL

/*
 * processor configuration
 *
 */

#define NIOS2_CPU_IMPLEMENTATION "small"
#define NIOS2_BIG_ENDIAN 0

#define NIOS2_ICACHE_SIZE 4096
#define NIOS2_DCACHE_SIZE 0
#define NIOS2_ICACHE_LINE_SIZE 32
#define NIOS2_ICACHE_LINE_SIZE_LOG2 5
#define NIOS2_DCACHE_LINE_SIZE 0
#define NIOS2_DCACHE_LINE_SIZE_LOG2 0
#define NIOS2_FLUSHDA_SUPPORTED

#define NIOS2_EXCEPTION_ADDR 0x00000020
#define NIOS2_RESET_ADDR 0x00000000
#define NIOS2_BREAK_ADDR 0x00808020

#define NIOS2_HAS_DEBUG_STUB

#define NIOS2_CPU_ID_SIZE 1
#define NIOS2_CPU_ID_VALUE 0

/*
 * A define for each class of peripheral
 *
 */

#define __ALTERA_AVALON_JTAG_UART
#define __ALTERA_AVALON_ONCHIP_MEMORY2
#define __ALTERA_AVALON_NEW_SDRAM_CONTROLLER
#define __ALTERA_AVALON_PIO
#define __ALTERA_AVALON_TIMER
#define __ALTERA_AVALON_SYSID

/*
 * jtag_uart_0 configuration
 *
 */

#define JTAG_UART_0_NAME "/dev/jtag_uart_0"
#define JTAG_UART_0_TYPE "altera_avalon_jtag_uart"
#define JTAG_UART_0_BASE 0x00808910
#define JTAG_UART_0_SPAN 8
#define JTAG_UART_0_IRQ 0
#define JTAG_UART_0_WRITE_DEPTH 64
#define JTAG_UART_0_READ_DEPTH 64
#define JTAG_UART_0_WRITE_THRESHOLD 8
#define JTAG_UART_0_READ_THRESHOLD 8
#define JTAG_UART_0_READ_CHAR_STREAM ""
#define JTAG_UART_0_SHOWASCII 1
#define JTAG_UART_0_READ_LE 0
#define JTAG_UART_0_WRITE_LE 0
#define JTAG_UART_0_ALTERA_SHOW_UNRELEASED_JTAG_UART_FEATURES 0
#define ALT_MODULE_CLASS_jtag_uart_0 altera_avalon_jtag_uart

/*
 * sram configuration
 *
 */

#define SRAM_NAME "/dev/sram"
#define SRAM_TYPE "altera_avalon_onchip_memory2"
#define SRAM_BASE 0x00800000
#define SRAM_SPAN 18432
#define SRAM_ALLOW_MRAM_SIM_CONTENTS_ONLY_FILE 0
#define SRAM_RAM_BLOCK_TYPE "M4K"
#define SRAM_INIT_CONTENTS_FILE "sram"
#define SRAM_NON_DEFAULT_INIT_FILE_ENABLED 0
#define SRAM_GUI_RAM_BLOCK_TYPE "Automatic"
#define SRAM_WRITEABLE 1
#define SRAM_DUAL_PORT 0
#define SRAM_SIZE_VALUE 18
#define SRAM_SIZE_MULTIPLE 1024
#define SRAM_CONTENTS_INFO "SIMDIR/sram.dat 1216478643 QUARTUS_PROJECT_DIR/sram.hex 1216478643 SIMDIR/onchip_memory_0.dat 1216477564 QUARTUS_PROJECT_DIR/onchip_memory_0.hex 1216477565"
#define ALT_MODULE_CLASS_sram altera_avalon_onchip_memory2

/*
 * sdram_0 configuration
 *
 */

#define SDRAM_0_NAME "/dev/sdram_0"
#define SDRAM_0_TYPE "altera_avalon_new_sdram_controller"
#define SDRAM_0_BASE 0x00000000
#define SDRAM_0_SPAN 8388608
#define SDRAM_0_REGISTER_DATA_IN 1
#define SDRAM_0_SIM_MODEL_BASE 1
#define SDRAM_0_SDRAM_DATA_WIDTH 16
#define SDRAM_0_SDRAM_ADDR_WIDTH 12
#define SDRAM_0_SDRAM_ROW_WIDTH 12
#define SDRAM_0_SDRAM_COL_WIDTH 8
#define SDRAM_0_SDRAM_NUM_CHIPSELECTS 1
#define SDRAM_0_SDRAM_NUM_BANKS 4
#define SDRAM_0_REFRESH_PERIOD 15.625
#define SDRAM_0_POWERUP_DELAY 100
#define SDRAM_0_CAS_LATENCY 3
#define SDRAM_0_T_RFC 70
#define SDRAM_0_T_RP 20
#define SDRAM_0_T_MRD 3
#define SDRAM_0_T_RCD 20
#define SDRAM_0_T_AC 6
#define SDRAM_0_T_WR 20
#define SDRAM_0_INIT_REFRESH_COMMANDS 2
#define SDRAM_0_INIT_NOP_DELAY 0
#define SDRAM_0_SHARED_DATA 0
#define SDRAM_0_STARVATION_INDICATOR 0
#define SDRAM_0_TRISTATE_BRIDGE_SLAVE ""
#define SDRAM_0_IS_INITIALIZED 1
#define SDRAM_0_SDRAM_BANK_WIDTH 2
#define SDRAM_0_CONTENTS_INFO "SIMDIR/sdram_0.dat 1216903258"
#define ALT_MODULE_CLASS_sdram_0 altera_avalon_new_sdram_controller

/*
 * led_pio configuration
 *
 */

#define LED_PIO_NAME "/dev/led_pio"
#define LED_PIO_TYPE "altera_avalon_pio"
#define LED_PIO_BASE 0x00808820
#define LED_PIO_SPAN 16
#define LED_PIO_DO_TEST_BENCH_WIRING 0
#define LED_PIO_DRIVEN_SIM_VALUE 0x0000
#define LED_PIO_HAS_TRI 0
#define LED_PIO_HAS_OUT 1
#define LED_PIO_HAS_IN 0
#define LED_PIO_CAPTURE 0
#define LED_PIO_EDGE_TYPE "NONE"
#define LED_PIO_IRQ_TYPE "NONE"
#define LED_PIO_FREQ 100000000
#define ALT_MODULE_CLASS_led_pio altera_avalon_pio

/*
 * timer_0 configuration
 *
 */

#define TIMER_0_NAME "/dev/timer_0"
#define TIMER_0_TYPE "altera_avalon_timer"
#define TIMER_0_BASE 0x00808800
#define TIMER_0_SPAN 32
#define TIMER_0_IRQ 1
#define TIMER_0_ALWAYS_RUN 0
#define TIMER_0_FIXED_PERIOD 0
#define TIMER_0_SNAPSHOT 1
#define TIMER_0_PERIOD 10
#define TIMER_0_PERIOD_UNITS "ms"
#define TIMER_0_RESET_OUTPUT 0
#define TIMER_0_TIMEOUT_PULSE_OUTPUT 0
#define TIMER_0_MULT 0.001
#define TIMER_0_FREQ 100000000
#define ALT_MODULE_CLASS_timer_0 altera_avalon_timer

/*
 * P0 configuration
 *
 */

#define P0_NAME "/dev/P0"
#define P0_TYPE "altera_avalon_pio"
#define P0_BASE 0x00808830
#define P0_SPAN 16
#define P0_DO_TEST_BENCH_WIRING 0
#define P0_DRIVEN_SIM_VALUE 0x0000
#define P0_HAS_TRI 0
#define P0_HAS_OUT 1
#define P0_HAS_IN 0
#define P0_CAPTURE 0
#define P0_EDGE_TYPE "NONE"
#define P0_IRQ_TYPE "NONE"
#define P0_FREQ 100000000
#define ALT_MODULE_CLASS_P0 altera_avalon_pio

/*
 * P1 configuration
 *
 */

#define P1_NAME "/dev/P1"
#define P1_TYPE "altera_avalon_pio"
#define P1_BASE 0x00808840
#define P1_SPAN 16
#define P1_DO_TEST_BENCH_WIRING 0
#define P1_DRIVEN_SIM_VALUE 0x0000
#define P1_HAS_TRI 0
#define P1_HAS_OUT 1
#define P1_HAS_IN 0
#define P1_CAPTURE 0
#define P1_EDGE_TYPE "NONE"
#define P1_IRQ_TYPE "NONE"
#define P1_FREQ 100000000
#define ALT_MODULE_CLASS_P1 altera_avalon_pio

/*
 * P2_0 configuration
 *
 */

#define P2_0_NAME "/dev/P2_0"
#define P2_0_TYPE "altera_avalon_pio"
#define P2_0_BASE 0x00808850
#define P2_0_SPAN 16
#define P2_0_DO_TEST_BENCH_WIRING 0
#define P2_0_DRIVEN_SIM_VALUE 0x0000
#define P2_0_HAS_TRI 0
#define P2_0_HAS_OUT 1
#define P2_0_HAS_IN 0
#define P2_0_CAPTURE 0
#define P2_0_EDGE_TYPE "NONE"
#define P2_0_IRQ_TYPE "NONE"
#define P2_0_FREQ 100000000
#define ALT_MODULE_CLASS_P2_0 altera_avalon_pio

/*
 * P2_1 configuration
 *
 */

#define P2_1_NAME "/dev/P2_1"
#define P2_1_TYPE "altera_avalon_pio"
#define P2_1_BASE 0x00808860
#define P2_1_SPAN 16
#define P2_1_DO_TEST_BENCH_WIRING 0
#define P2_1_DRIVEN_SIM_VALUE 0x0000
#define P2_1_HAS_TRI 0
#define P2_1_HAS_OUT 1
#define P2_1_HAS_IN 0
#define P2_1_CAPTURE 0
#define P2_1_EDGE_TYPE "NONE"
#define P2_1_IRQ_TYPE "NONE"
#define P2_1_FREQ 100000000
#define ALT_MODULE_CLASS_P2_1 altera_avalon_pio

/*
 * P2_2 configuration
 *
 */

#define P2_2_NAME "/dev/P2_2"
#define P2_2_TYPE "altera_avalon_pio"
#define P2_2_BASE 0x00808870
#define P2_2_SPAN 16
#define P2_2_DO_TEST_BENCH_WIRING 0
#define P2_2_DRIVEN_SIM_VALUE 0x0000
#define P2_2_HAS_TRI 0
#define P2_2_HAS_OUT 1
#define P2_2_HAS_IN 0
#define P2_2_CAPTURE 0
#define P2_2_EDGE_TYPE "NONE"
#define P2_2_IRQ_TYPE "NONE"
#define P2_2_FREQ 100000000
#define ALT_MODULE_CLASS_P2_2 altera_avalon_pio

/*
 * P2_3 configuration
 *
 */

#define P2_3_NAME "/dev/P2_3"
#define P2_3_TYPE "altera_avalon_pio"
#define P2_3_BASE 0x00808880
#define P2_3_SPAN 16
#define P2_3_DO_TEST_BENCH_WIRING 0
#define P2_3_DRIVEN_SIM_VALUE 0x0000
#define P2_3_HAS_TRI 0
#define P2_3_HAS_OUT 1
#define P2_3_HAS_IN 0
#define P2_3_CAPTURE 0
#define P2_3_EDGE_TYPE "NONE"
#define P2_3_IRQ_TYPE "NONE"
#define P2_3_FREQ 100000000
#define ALT_MODULE_CLASS_P2_3 altera_avalon_pio

/*
 * P2_4 configuration
 *
 */

#define P2_4_NAME "/dev/P2_4"
#define P2_4_TYPE "altera_avalon_pio"
#define P2_4_BASE 0x00808890
#define P2_4_SPAN 16
#define P2_4_DO_TEST_BENCH_WIRING 0
#define P2_4_DRIVEN_SIM_VALUE 0x0000
#define P2_4_HAS_TRI 0
#define P2_4_HAS_OUT 1
#define P2_4_HAS_IN 0
#define P2_4_CAPTURE 0
#define P2_4_EDGE_TYPE "NONE"
#define P2_4_IRQ_TYPE "NONE"
#define P2_4_FREQ 100000000
#define ALT_MODULE_CLASS_P2_4 altera_avalon_pio

/*
 * P2_5 configuration
 *
 */

#define P2_5_NAME "/dev/P2_5"
#define P2_5_TYPE "altera_avalon_pio"
#define P2_5_BASE 0x008088A0
#define P2_5_SPAN 16
#define P2_5_DO_TEST_BENCH_WIRING 0
#define P2_5_DRIVEN_SIM_VALUE 0x0000
#define P2_5_HAS_TRI 0
#define P2_5_HAS_OUT 1
#define P2_5_HAS_IN 0
#define P2_5_CAPTURE 0
#define P2_5_EDGE_TYPE "NONE"
#define P2_5_IRQ_TYPE "NONE"
#define P2_5_FREQ 100000000
#define ALT_MODULE_CLASS_P2_5 altera_avalon_pio

/*
 * P2_6 configuration
 *
 */

#define P2_6_NAME "/dev/P2_6"
#define P2_6_TYPE "altera_avalon_pio"
#define P2_6_BASE 0x008088B0
#define P2_6_SPAN 16
#define P2_6_DO_TEST_BENCH_WIRING 0
#define P2_6_DRIVEN_SIM_VALUE 0x0000
#define P2_6_HAS_TRI 0
#define P2_6_HAS_OUT 1
#define P2_6_HAS_IN 0
#define P2_6_CAPTURE 0
#define P2_6_EDGE_TYPE "NONE"
#define P2_6_IRQ_TYPE "NONE"
#define P2_6_FREQ 100000000
#define ALT_MODULE_CLASS_P2_6 altera_avalon_pio

/*
 * P2_7 configuration
 *
 */

#define P2_7_NAME "/dev/P2_7"
#define P2_7_TYPE "altera_avalon_pio"
#define P2_7_BASE 0x008088C0
#define P2_7_SPAN 16
#define P2_7_DO_TEST_BENCH_WIRING 0
#define P2_7_DRIVEN_SIM_VALUE 0x0000
#define P2_7_HAS_TRI 0
#define P2_7_HAS_OUT 1
#define P2_7_HAS_IN 0
#define P2_7_CAPTURE 0
#define P2_7_EDGE_TYPE "NONE"
#define P2_7_IRQ_TYPE "NONE"
#define P2_7_FREQ 100000000
#define ALT_MODULE_CLASS_P2_7 altera_avalon_pio

/*
 * PWM configuration
 *
 */

#define PWM_NAME "/dev/PWM"
#define PWM_TYPE "altera_avalon_pio"
#define PWM_BASE 0x008088D0
#define PWM_SPAN 16
#define PWM_DO_TEST_BENCH_WIRING 0
#define PWM_DRIVEN_SIM_VALUE 0x0000
#define PWM_HAS_TRI 0
#define PWM_HAS_OUT 1
#define PWM_HAS_IN 0
#define PWM_CAPTURE 0
#define PWM_EDGE_TYPE "NONE"
#define PWM_IRQ_TYPE "NONE"
#define PWM_FREQ 100000000
#define ALT_MODULE_CLASS_PWM altera_avalon_pio

/*
 * P3_3 configuration
 *
 */

#define P3_3_NAME "/dev/P3_3"
#define P3_3_TYPE "altera_avalon_pio"
#define P3_3_BASE 0x008088E0
#define P3_3_SPAN 16
#define P3_3_DO_TEST_BENCH_WIRING 0
#define P3_3_DRIVEN_SIM_VALUE 0x0000
#define P3_3_HAS_TRI 0
#define P3_3_HAS_OUT 0
#define P3_3_HAS_IN 1
#define P3_3_CAPTURE 0
#define P3_3_EDGE_TYPE "NONE"
#define P3_3_IRQ_TYPE "NONE"
#define P3_3_FREQ 100000000
#define ALT_MODULE_CLASS_P3_3 altera_avalon_pio

/*
 * P3_4 configuration
 *
 */

#define P3_4_NAME "/dev/P3_4"
#define P3_4_TYPE "altera_avalon_pio"
#define P3_4_BASE 0x008088F0
#define P3_4_SPAN 16
#define P3_4_DO_TEST_BENCH_WIRING 0
#define P3_4_DRIVEN_SIM_VALUE 0x0000
#define P3_4_HAS_TRI 0
#define P3_4_HAS_OUT 0
#define P3_4_HAS_IN 1
#define P3_4_CAPTURE 0
#define P3_4_EDGE_TYPE "NONE"
#define P3_4_IRQ_TYPE "NONE"
#define P3_4_FREQ 100000000
#define ALT_MODULE_CLASS_P3_4 altera_avalon_pio

/*
 * P3_5 configuration
 *
 */

#define P3_5_NAME "/dev/P3_5"
#define P3_5_TYPE "altera_avalon_pio"
#define P3_5_BASE 0x00808900
#define P3_5_SPAN 16
#define P3_5_DO_TEST_BENCH_WIRING 0
#define P3_5_DRIVEN_SIM_VALUE 0x0000
#define P3_5_HAS_TRI 0
#define P3_5_HAS_OUT 0
#define P3_5_HAS_IN 1
#define P3_5_CAPTURE 0
#define P3_5_EDGE_TYPE "NONE"
#define P3_5_IRQ_TYPE "NONE"
#define P3_5_FREQ 100000000
#define ALT_MODULE_CLASS_P3_5 altera_avalon_pio

/*
 * sysid configuration
 *
 */

#define SYSID_NAME "/dev/sysid"
#define SYSID_TYPE "altera_avalon_sysid"
#define SYSID_BASE 0x00808918
#define SYSID_SPAN 8
#define SYSID_ID 3856277363u
#define SYSID_TIMESTAMP 1217156276u
#define ALT_MODULE_CLASS_sysid altera_avalon_sysid

/*
 * system library configuration
 *
 */

#define ALT_MAX_FD 32
#define ALT_SYS_CLK none
#define ALT_TIMESTAMP_CLK none

/*
 * Devices associated with code sections.
 *
 */

#define ALT_TEXT_DEVICE       SDRAM_0
#define ALT_RODATA_DEVICE     SDRAM_0
#define ALT_RWDATA_DEVICE     SDRAM_0
#define ALT_EXCEPTIONS_DEVICE SDRAM_0
#define ALT_RESET_DEVICE      SDRAM_0

/*
 * The text section is initialised so no bootloader will be required.
 * Set a variable to tell crt0.S to provide code at the reset address and
 * to initialise rwdata if appropriate.
 */

#define ALT_NO_BOOTLOADER


#endif /* __SYSTEM_H_ */