📄 _lt133x2_124.h
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///////////////////////////////////////////////////////////////////
// Definitions for Display Port
#define SINGLE_PORT 0x00 // Single port (Single pixel output)
#define DOUBLE_PORT 0x04 // Double port (Double pixel output)
#define DISPLAY_PORT SINGLE_PORT
///////////////////////////////////////////////////////////////////
// Definitions for Display Color
#define DISP_18BIT 0x10 // 18-bit RGB output
#define DISP_24BIT 0x00 // 24-bit RGB output
#define DISP_BIT DISP_18BIT
///////////////////////////////////////////////////////////////////
// Definitions for Display Timing Feature
#define MASK_FIRST_DHS 0x80 // Mask 1st DHS
#define NO_MASKING 0x00 // No masking
#define DHS_MASK NO_MASKING
///////////////////////////////////////////////////////////////////
// Definitions for Display Signal
#define DISP_INV 0x0C // DVS : neg , DHS : neg , DEN : pos
#define DCLK_INV 0x08 // DCLK : pos
#define DCLK_DELAY 0x03 // 1.0ns delay for DCLK
///////////////////////////////////////////////////////////////////
// Definitions for Display Settings
#define MAX_DCLK 94 // Maximum display clock rate in MHz that panel can support
#define MAX_RATE 78 // Maximum display refresh rate in Hz that panel can support
#define DH_ACT_STA_POS 0x0020 // DH_ACT_STA_POS should be as small as possible !!!
#define DH_ACT_END_POS 0x0420
#define DV_ACT_STA_POS 0x000c // DV_ACT_STA_POS should be as small as possible !!!
#define DV_ACT_END_POS 0x030c
#define DISP_WID (DH_ACT_END_POS - DH_ACT_STA_POS) // 0x0400 = 1024 pixels
#define DISP_LEN (DV_ACT_END_POS - DV_ACT_STA_POS) // 0x0300 = 768 lines
#define STD_DH_TOTAL 0x04a0 // Standard display clock number in one display horizontal line
#define STD_DV_TOTAL 0x0360 // Standard display horizontal line in one display frame
#define STD_HSYNC_WIDTH 0x10 // Display HSYNC clock width
#define STD_VSYNC_LENGTH 0x03 // Display VSYNC line length
#define MIN_DV_TOTAL 0x310 // Minimum VSYNC that panel can support
#define MIN_LAST_DHT 0x190 // Must set to 0 if you don't care last-line length
#define MAX_LAST_DHT 0 // Set it to 0 if you don't care the maximum last-line length
#define VIDEO_ML_DHT 0x190 // Minimum last-line length for video
#define USER_MODE_NCODE 20 // NEVER change this setting !!!
#define DISP_ALIGN 0 // 0-Left alignment, 1-Right alignment
#define AUTO_SWITCH 0x60 // Auto Switch to freerun mode
/////////////////////////////////////////////////////////////////// //V212
// Definitions for display size and type
#define DISP_480x234 0 // 0: 480x234
#define DISP_640x480 1 // 1: 640X480
#define DISP_800x600 2 // 2: 800x600
#define DISP_1024x768 3 // 3: 1024x768
#define DISP_1280x768 4 // 4: 1280x768
#define DISP_1280x800 5 // 5: 1280x800
#define DISP_1280x1024 6 // 6: 1280X1024
#define DISP_1400x1050 7 // 7: 1400X1050
#define DISP_1680x1050 8 // 8: 1680X1050
#define DISP_1600x1200 9 // 9: 1280X1024
#define DISP_SIZE DISP_1024x768
#define PANEL_2E 1 // 1 DV_TOTAL_H_2E = 0 0 DV_TOTAL_H_2E != 0
#define TTL_TYPE 0
#define LVDS_TYPE 1
#define RSDS_TYPE 2
#define OUTPUT_BUS LVDS_TYPE
#if(OUTPUT_BUS == LVDS_TYPE)
#define LVDS_MAP1 0 //LVDS Bit-Mapping Table 1
#define LVDS_MAP2 1 //LVDS Bit-Mapping Table 2
#define LVDS_MAP LVDS_MAP2
#endif
#define SWAP_RED_BLUE 0 // 0 : Normal; 1 : Swap Red and Blue
#define SWAP_ODD_EVEN 0 // 0 :83-93 1 : A3-B3
//---------------------------------- 1024x768 ---------------------------------
///////////////////////////////////////////////////////////////////////////
#ifdef __MAIN__
unsigned char code RTD_PWUP_INI[] =
{
5, Y_INC, HOSTCTRL_02, 0x42,0x00,
4, N_INC, TC_ADDR_PORT_95, 0x00,
7, N_INC, TC_DATA_PORT_96, 0x00,0x00,0x00,0x00,
9, Y_INC, GP1_ODOCTRL_F6, 0x00,0x00,0x00,0x00,0x00,0x00,
6, Y_INC, IRQ_CTRL1_0E, 0x00,0x80,0x00,
4, N_INC, INT_FLD_DETECT_14, 0x00,
25, Y_INC, DH_TOTAL_22, 0x08,0x00,0x02,0x04,0x00,0x04,0x00,0x06,0x00,0x06,0x00,
0x06,0x00,0x01,0x02,0x00,0x02,0x00,0x04,0x00,0x04,0x00,
6, Y_INC, YUV2RGB_39, 0x00,0x00,0x00,
5, Y_INC, DUTY_FINE_TUNE_3E, 0xc0,0x0e, // For improving display speed
4, N_INC, MEAS_HS_LATCH_4E, 0x00,
5, Y_INC, CLAMP_55, 0x04,0x10,
4, N_INC, COLOR_CTRL_5D, 0x03,
4, N_INC, OP_CRC_CTRL_68, 0x88,
#if(SWAP_ODD_EVEN) //V212
#if (SWAP_RED_BLUE)
6, Y_INC, PATTERN_GEN_6C, 0x00,0xB3,0x00,
#else
6, Y_INC, PATTERN_GEN_6C, 0x00,0xA3,0x00,
#endif
#else
#if (SWAP_RED_BLUE)
6, Y_INC, PATTERN_GEN_6C, 0x00,0x93,0x00,
#else
6, Y_INC, PATTERN_GEN_6C, 0x00,0x83,0x00,
#endif
#endif //#if(SWAP_ODD_EVEN)
4, N_INC, SD_CTRL_70, 0x00,
6, Y_INC, IVS_DELAY_8C, 0x00,0x00,0x00,
7, Y_INC, PLL_DIV_CTRL0_C8, 0x04,0x00,0x20,0x18,
8, Y_INC, DPLL_CTRL_D0, 0x11,0x63,0x52,0x2f,0x06, // DCLK=62.5MHz
13, Y_INC, PLL1_CTRL_D6, 0xf2,0x11,0x00,0x7f,0x30,0x0a,0x04,0x3f,0xff,0x81,
4, N_INC, ADC_CTRL_E6, 0x40,
4, ADC_REG_CLK_EA, 0x05,0x02,
9, Y_INC, TMDS_OUTPUT_ENA_A0, 0x0f, 0xef,0x8b,0x26,0x35,0x2f,
0
};
unsigned char code RTD_DDC_TABLE[] =
{
5, Y_INC, DDC_ENABLE_FC, 0x00,0x00, // Disable the DDC channel
131, N_INC, DDC_ACCESS_P_FE, 0x00,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0x00,
0x4A,0x8B,0x01,0x00,0x01,0x01,0x01,0x01,
0x0C,0x0F,0x01,0x03,0x6E,0x1E,0x14,0x78,
0xE8,0xCA,0x01,0x9A,0x58,0x52,0x8B,0x28,
0x1E,0x50,0x54,0xAD,0xCE,0x00,0x01,0x01,
0x01,0x01,0x01,0x01,0x01,0x01,0x01,0x01,
0x01,0x01,0x01,0x01,0x01,0x01,0x64,0x19,
0x00,0x40,0x41,0x00,0x26,0x30,0x10,0x88,
0x36,0x00,0x67,0x1F,0x11,0x00,0x00,0x38,
0x00,0x00,0x00,0xFC,0x00,0x4C,0x43,0x44,
0x20,0x31,0x35,0x0A,0x0A,0x0A,0x0A,0x0A,
0x0A,0x0A,0x00,0x00,0x00,0xFD,0x00,0x3A,
0x4B,0x1E,0x41,0x0B,0x00,0x0A,0x20,0x20,
0x20,0x20,0x20,0x20,0x00,0x00,0x00,0x10,
0x00,0x30,0x30,0x30,0x30,0x30,0x31,0x0A,
0x20,0x20,0x20,0x20,0x20,0x20,0x00,0xC1,
4, N_INC, DDC_ENABLE_FC, 0x05, // Enable the DDC channel
#if(TMDS_ENABLE)
5, Y_INC, DDC_ENABLE_BC, 0x00,0x00, // Disable the DDC channel of DVI
131, N_INC, DDC_ACCESS_PORT_BE, 0x00,0xff,0xff,0xff,0xff,0xff,0xff,0x00,
0x26,0xCD,0x68,0x46,0x00,0x00,0x00,0x00,
0x23,0x0c,0x01,0x03,0x81,0x24,0x1D,0x78,
0xeF,0x0D,0xC2,0xa0,0x57,0x47,0x98,0x27,
0x12,0x48,0x4F,0xBF,0xEF,0x00,0x81,0x80,
0x81,0x8F,0x61,0x40,0x61,0x59,0x45,0x40,
0x45,0x59,0x31,0x40,0x31,0x59,0xBC,0x34,
0x00,0x98,0x51,0x00,0x2A,0x40,0x10,0x90,
0x13,0x00,0x68,0x22,0x11,0x00,0x00,0x1e,
0x00,0x00,0x00,0xFF,0x00,0x30,0x0A,0x20,
0x20,0x20,0x20,0x20,0x20,0x20,0x20,0x20,
0x20,0x20,0x00,0x00,0x00,0xFC,0x00,0x41,
0x53,0x34,0x36,0x33,0x37,0x20,0x20,0x20,
0x20,0x20,0x20,0x20,0x00,0x00,0x00,0xFD,
0x00,0x38,0x55,0x18,0x50,0x0E,0x00,0x0A,
0x20,0x20,0x20,0x20,0x20,0x20,0x00,0x06,
4, N_INC, DDC_ENABLE_BC, 0x05, // Enable the DDC channel of DVI
#endif
0
};
unsigned char code RTD_IO_INI[] =
{
4, N_INC, TC_ADDR_PORT_95, 0x00,
7, N_INC, TC_DATA_PORT_96, 0x40,0x30,0x33,0x08,
#if(OUTPUT_BUS == LVDS_TYPE)
#if(LVDS_MAP1 == LVDS_MAP)
8, Y_INC, LVDS_CTRL0_C0, 0x00,0xa3,0x22,0x80,0x80,
#else
8, Y_INC, LVDS_CTRL0_C0, 0x00,0xa3,0x23,0x80,0x80,
#endif
#endif
0
};
// Be Careful !!
// Display window setting in FreeV[] MUST follow the definition of
// 1. DISP_WID and DISP_LEN
// 2. DH_ACT_STA_POS and DH_ACT_END_POS
// 3. DV_ACT_STA_POS and DV_ACT_END_POS
// 4. Background window must be the same as active window.
unsigned char code FreeV[] =
{
#if (SPREAD_SPECTRUM)
4, N_INC, DPLL_CTRL_D0, 0x09, // Enable DCLK
#else
4, N_INC, DPLL_CTRL_D0, 0x11, // Enable DCLK
#endif
27, Y_INC, VDIS_CTRL_20, 0x21 | DISP_BIT | DISPLAY_PORT, // Disable display timing
DISP_INV,
(STD_DH_TOTAL & 0xff), (STD_DH_TOTAL >> 8), // DH_TOTAL
STD_HSYNC_WIDTH, // DH_HS_END
(DH_ACT_STA_POS & 0xff), (DH_ACT_STA_POS >> 8), // DH_BKGD_STA
(DH_ACT_STA_POS & 0xff), (DH_ACT_STA_POS >> 8), // DH_ACT_STA
(DH_ACT_END_POS & 0xff), (DH_ACT_END_POS >> 8), // DH_ACT_END
(DH_ACT_END_POS & 0xff), (DH_ACT_END_POS >> 8), // DH_BKGD_END
(STD_DV_TOTAL & 0xff), (STD_DV_TOTAL >> 8), // DV_TOTAL
STD_VSYNC_LENGTH, // DV_VS_END
(DV_ACT_STA_POS & 0xff), (DV_ACT_STA_POS >> 8) | AUTO_SWITCH, // DV_BKGD_STA
(DV_ACT_STA_POS & 0xff), (DV_ACT_STA_POS >> 8), // DV_ACT_STA
(DV_ACT_END_POS & 0xff), (DV_ACT_END_POS >> 8), // DV_ACT_END
(DV_ACT_END_POS & 0xff), (DV_ACT_END_POS >> 8), // DV_BKGD_END
4, N_INC, VDIS_CTRL_20, 0x23 | DISP_BIT | DISPLAY_PORT, // Enable free-run background
// Force display timing start
6, Y_INC, YUV2RGB_39, 0x00, 0x20 | DCLK_DELAY, 0x04 | DCLK_INV,
4, N_INC, DIS_TIMING0_3A, 0x00 | DCLK_DELAY,
4, N_INC, INT_FLD_DETECT_14, 0x00,
5, Y_INC, IVS_DELAY_8C, 0x00, 0x00,
4, N_INC, SCALE_CTRL_15, 0x00,
4, N_INC, FILTER_CTRL0_1B, 0xc4,
0
};
unsigned char code OSD_PWUP_INI[] =
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