📄 lcd_main.lst
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804 2 // Original Formula :
805 2 // ucRefresh = 24.576M / (usHsync * usVsync)
806 2 // Use Data[0~3] as a temporary long variable
807 2 ((unsigned long *)Data)[0] = (unsigned long)usHsync * usVsync;
808 2 ucRefresh = (unsigned long)49152000 / ((unsigned long *)Data)[0];
809 2 ucRefresh = (ucRefresh & 0x01) ? ((ucRefresh + 1) >> 1) : (ucRefresh >> 1);
810 2
811 2 // Treat small change of usHsync/usVsync as no change
812 2 if (usStdHS <= usHsync && (usStdHS + 2) >= usHsync) usHsync = usStdHS;
813 2 if (usStdVS <= usVsync && (usStdVS + 2) >= usVsync) usVsync = usStdVS;
814 2
815 2 // Polarity must be correct
816 2 if ((bVpole_Curr != bVpole_Prev) || (bHpole_Curr != bHpole_Prev))
817 2 {
818 3 RTDRead(VGIP_SIGINV_05, 0x01, N_INC);
819 3
820 3 Data[0] &= 0xd7; // HS_RAW & VS positive
821 3
822 3 if (!bHpole_Curr) Data[0] |= 0x20;
823 3
824 3 if (!bVpole_Curr && SYNC_SS == ucSync_Type) Data[0] |= 0x08; // Seperate sync
825 3
826 3 RTDSetByte(VGIP_SIGINV_05, Data[0]);
827 3
828 3 ucMode_Temp = MODE_NOSUPPORT;
829 3 }
830 2 else
831 2 {
832 3 if (0x07ff <= usHsync || 0x07ff <= usVsync || 0 == usHsync || 0 == usVsync)
833 3 {
834 4 ucMode_Temp = MODE_NOSIGNAL; // Treat overflow as no signal
835 4 }
836 3 else
837 3 {
838 4 Data[0] = usHS_Pulse * 12 / usHsync; // 0 : 720x350; 1 : 640x350;
839 4
840 4 ucMode_Temp = MODE_NOSUPPORT;
841 4
842 4 // Search for Standard Mode
843 4 #if(DISP_SIZE <= DISP_1024x768) //V225
844 4 m = MODE_1024x0768x75HZ;
845 4 #endif
846 4 #if(DISP_SIZE == DISP_1280x1024)
m = MODE_1280x1024x75HZ;
#endif
849 4 #if(DISP_SIZE > DISP_1280x1024)
m = MODE_1600x1200x60HZ;
#endif
852 4
853 4 do
854 4 {
855 5 if ((usHsync > VGA_Mode[m][0]) && (usHsync < VGA_Mode[m][1]))
856 5 {
857 6 if ((usVsync >= VGA_Mode[m][2]) && (usVsync <= VGA_Mode[m][3]))
858 6 {
859 7 if (MODE_1280x1024x75HZ == m)
C51 COMPILER V7.50 LCD_MAIN 07/28/2008 16:10:53 PAGE 15
860 7 {
861 8 if (0 == (bVpole_Curr | bHpole_Curr)) m = MODE_1280x1024x76HZ; // SUN
- 1024-76
862 8 }
863 7 else if (MODE_1024x0768x75HZ == m)
864 7 {
865 8 if (0 == (bVpole_Curr | bHpole_Curr)) m = MODE_1024x0768x74HZ; // MAC
-768-75
866 8 }
867 7 else if (MODE_0640x0480x60HZ == m && bVpole_Curr != bHpole_Curr)
868 7 {
869 8 // MODE_VGA350x60Hz : 640x350 60Hz
870 8 // MODE_VGA350x60Hz | 0x40 : 720x350 60Hz
871 8 // MODE_VGA400x60Hz : 640x400 60Hz
872 8 // MODE_VGA400x60Hz | 0x40 : 720x400 60Hz
873 8 if (bHpole_Curr)
874 8 m = Data[0] ? MODE_VGA350x60Hz : MODE_VGA350x60Hz | 0x40;
875 8 else
876 8 m = (stGUD1.INPUT_SOURCE & 0x80) ? MODE_VGA400x60Hz : MODE_VGA400x60
-Hz | 0x40;
877 8 }
878 7 else if (MODE_0640x0480x50HZ == m && bVpole_Curr != bHpole_Curr)
879 7 {
880 8 // MODE_VGA350x50Hz : 640x350 50Hz
881 8 // MODE_VGA350x50Hz | 0x40 : 720x350 50Hz
882 8 // MODE_VGA400x50Hz : 640x400 50Hz
883 8 // MODE_VGA400x50Hz | 0x40 : 720x400 50Hz
884 8 if (bHpole_Curr)
885 8 m = Data[0] ? MODE_VGA350x50Hz : MODE_VGA350x50Hz | 0x40;
886 8 else
887 8 m = (stGUD1.INPUT_SOURCE & 0x80) ? MODE_VGA400x50Hz : MODE_VGA400x50
-Hz | 0x40;
888 8 }
889 7 else if (MODE_0720x0400x85HZ == m)
890 7 {
891 8 if (1 == bHpole_Curr && 0 == bVpole_Curr)
892 8 m = MODE_0640x0350x85HZ;
893 8 else if (stGUD1.INPUT_SOURCE & 0x80)
894 8 m = MODE_0640x0400x85HZ;
895 8 }
896 7 else if (MODE_0720x0400x70HZ == m)
897 7 {
898 8 if (1 == bHpole_Curr && 0 == bVpole_Curr)
899 8 m = Data[0] ? MODE_0640x0350x70HZ : MODE_0720x0350x70HZ;
900 8 else if (stGUD1.INPUT_SOURCE & 0x80)
901 8 m = MODE_0640x0400x70HZ;
902 8 }
903 7
904 7 ucMode_Temp = m;
905 7 }
906 6 }
907 5 }
908 4 while ((0 != --m) && (MODE_NOSUPPORT == ucMode_Temp));
909 4
910 4 // Search for User Mode
911 4 if (MODE_NOSUPPORT == ucMode_Temp)
912 4 {
913 5 usIPV_ACT_LEN = 0;
914 5
915 5 #if(DISP_SIZE <= DISP_1024x768) //V225
916 5 m = MODE_USER1024x768;
917 5 #endif
C51 COMPILER V7.50 LCD_MAIN 07/28/2008 16:10:53 PAGE 16
918 5 #if(DISP_SIZE == DISP_1280x1024)
m = MODE_USER1280x1024;
#endif
921 5 #if(DISP_SIZE > DISP_1280x1024)
m = MODE_USER1600x1200;
#endif
924 5
925 5 do
926 5 {
927 6 if ((usVsync >= VGA_Mode[m][2]) && (usVsync <= VGA_Mode[m][3]))
928 6 {
929 7 usIPV_ACT_LEN = CAP_WIN[m][4];
930 7
931 7 if ((usHsync >= VGA_Mode[m][0]) && (usHsync <= VGA_Mode[m][1]))
932 7 {
933 8 ucMode_Temp = m; // Support User Mode
934 8 }
935 7 }
936 6 }
937 5 while ((MODE_USER720x400 <= --m) && (MODE_NOSUPPORT == ucMode_Temp));
938 5 }
939 4
940 4 if (48 > ucRefresh || MAX_RATE < ucRefresh)
941 4 {
942 5 ucMode_Temp = MODE_NOSUPPORT; // We don't support vertical refresh rate lower than 5
-0Hz
943 5 }
944 4 else if (MODE_NOSUPPORT == ucMode_Temp && 0 != usIPV_ACT_LEN)
945 4 {
946 5 if (DISP_LEN < usIPV_ACT_LEN) // V Scale-down
947 5 {
948 6 // Estimate display clock rate for full screen
949 6 // DCLK = (24.576MHz / usHsync) * DCLK per display line * (display image lines / i
-nput image lines)
950 6 ((unsigned int *)Data)[0] = (unsigned long)2458 * Mode_Preset[MODE_UNDEFINED1][0
-] * DISP_LEN
951 6 / ((unsigned long)100 * usIPV_ACT_LEN * usHsync);
952 6
953 6 if (MAX_DCLK < ((unsigned int *)Data)[0])
954 6 {
955 7 // If clock rate for full-screen display is too high, we can try partial-V dis
-play.
956 7 // Estimate clock for partial-V display
957 7 // DCLK = (24.576MHz / usHsync) * DCLK per display line * (min. display total
-lines / input total lines)
958 7 ((unsigned int *)Data)[1] = (unsigned long)2458 * Mode_Preset[MODE_UNDEFINED
-1][0] * MIN_DV_TOTAL
959 7 / ((unsigned long)100 * (usVsync - 1) * usHsync);
960 7
961 7 if (MAX_DCLK < ((unsigned int *)Data)[1])
962 7 {
963 8 // Decrease usIPV_ACT_LEN to DISP_LEN and go further to check if it can be
- displayed.
964 8 usIPV_ACT_LEN = DISP_LEN;
965 8 }
966 7 else
967 7 {
968 8 ucMode_Temp = MODE_UNDEFINED1 | 0x80; // Scale-down and partial-V di
-splay
969 8 }
970 7 }
971 6 else
C51 COMPILER V7.50 LCD_MAIN 07/28/2008 16:10:53 PAGE 17
972 6 ucMode_Temp = MODE_UNDEFINED1; // Scale-down and full-V displ
-ay
973 6 }
974 5
975 5 if (DISP_LEN >= usIPV_ACT_LEN) // V Scale-up
976 5 {
977 6 ((unsigned int *)Data)[0] = (unsigned long)2458 * Mode_Preset[MODE_UNDEFINED0][0
-] * DISP_LEN
978 6 / ((unsigned long)100 * usIPV_ACT_LEN * usHsync);
979 6
980 6 if (MAX_DCLK < ((unsigned int *)Data)[0])
981 6 {
982 7 if (MIN_DV_TOTAL >= (usVsync - 1))
983 7 {
984 8 ((unsigned int *)Data)[1] = (unsigned long)2458 * Mode_Preset[MODE_UNDEF
-INED0][0] * MIN_DV_TOTAL
985 8 / ((unsigned long)100 * (usVsync - 1) * usHsyn
-c);
986 8 }
987 7 else
988 7 {
989 8 ((unsigned int *)Data)[1] = (unsigned long)2458 * Mode_Preset[MODE_UNDEF
-INED0][0]
990 8 / ((unsigned long)100 * usHsync);
991 8 }
992 7
993 7 if (MAX_DCLK < ((unsigned int *)Data)[1])
994 7 ucMode_Temp = MODE_NOSUPPORT; // Cannot display
995 7 else
996 7 ucMode_Temp = MODE_UNDEFINED0 | 0x80; // Scale-up and partial-V display
997 7 }
998 6 else
999 6 ucMode_Temp = MODE_UNDEFINED0; // Scale-up and full-V display
1000 6 }
1001 5 }
1002 4 }
1003 3 }
1004 2 }
1005 1
1006 1 if (SYNC_SOG == ucSync_Type && 0 != (usHS_Pulse * 7 / usHsync))
1007 1 {
1008 2 // To prevent from SOG mode mistake
1009 2 // HSYNC pulse width will never longer than 1/7*HSYNC period
1010 2 ucMode_Temp = MODE_NOSIGNAL;
1011 2 }
1012 1
1013 1 //-------------Check result--------------
1014 1 if (MODE_NOSUPPORT == ucMode_Temp || MODE_NOSIGNAL == ucMode_Temp)
1015 1 {
1016 2 // Treat illegal signal as no signal when SOG
1017 2 if (SYNC_SOG == ucSync_Type) ucMode_Temp = MODE_NOSIGNAL;
1018 2
1019 2 if (MODE_NOSUPPORT != ucMode_Found && MODE_NOSIGNAL != ucMode_Found) ucMode_Times = 0;
1020 2
1021 2 ucMode_Found = ucMode_Temp;
1022 2
1023 2 LED_GREEN = 0X00;
1024 2 LED_RED = 0X00;
1025 2
1026 2 if (NO_MODE_TIMES > ucMode_Times)
1027 2 {
1028 3 // Wait for signal stable
C51 COMPILER V7.50 LCD_MAIN 07/28/2008 16:10:53 PAGE 18
1029 3 ucMode_Times ++;
1030 3 }
1031 2 else
1032 2 {
1033 3 bStable = (ucMode_Curr == ucMode_Found) ? 1 : 0; // bStable must be cleared when mo
-de changed
1034 3 ucMode_Curr = ucMode_Found;
1035 3 ucMode_Times = NO_MODE_TIMES - 2;
1036 3
1037 3 if (MODE_NOSIGNAL == ucMode_Curr)
1038 3 {
1039 4 if (SYNC_CS == ucSync_Type) // CS->SS
1040 4 {
1041 5 RTDCodeW(VGA_SET_SS);
1042 5
1043 5 bVpole_Curr = 1;
1044 5 bHpole_Curr = 1;
1045 5 ucSync_Type = SYNC_SS;
1046 5 }
1047 4 else if (SYNC_SS == ucSync_Type) // SS->SOG
1048 4 {
1049 5 RTDCodeW(VGA_SET_SOG);
1050 5
1051 5 bVpole_Curr = 1;
1052 5 bHpole_Curr = 1;
1053 5 ucSync_Type = SYNC_SOG;
1054 5 }
1055 4 else // SOG->CS
1056 4 {
1057 5 RTDCodeW(VGA_SET_CS);
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