📄 lcd_main.c
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{
if (NO_MODE_TIMES < ucMode_Times)
{
bStable = 1; // Set bStable to 1 when signal timing is stable.
ucMode_Times = NO_MODE_TIMES - 1;
}
}
}
#endif
}
//------------------- Check AV Mode -------------------//
void Check_Video_Mode(void)
{
#if (VIDEO_CHIP == TW_9905)
if(SOURCE_TV == ucInputSrc)
{
if(ucMode_Curr==MODE_VIDEO50HZ)
{
if(Detect_Video_Signal( )==MODE_VIDEO60HZ)
{
ucMode_Curr = MODE_NOSIGNAL;
return;
}
if(Detect_Video_Signal( )==MODE_VIDEO50HZ)
{
if(bFreeRun)
{
RTDSetBit(VDIS_CTRL_20, 0xf6, 0x08);
RTDSetBit(VDIS_CTRL_20, 0xf6, 0x09);
bFreeRun=0;
}
}
}
else//60HZ
{
if(Detect_Video_Signal( )==MODE_VIDEO50HZ)
{
ucMode_Curr = MODE_NOSIGNAL;
return;
}
if(Detect_Video_Signal( )==MODE_VIDEO60HZ)
{
if(bFreeRun)
{
RTDSetBit(VDIS_CTRL_20, 0xf6, 0x08);
RTDSetBit(VDIS_CTRL_20, 0xf6, 0x09);
bFreeRun=0;
}
}
}
return;
}
Data[0]=I2CRead_TW990X(0x01);
if ((Data[0] & 0x80)==0)
{
Delay_Xms(10);
Data[0]=I2CRead_TW990X(0x1c);
Data[0]=Data[0]>>4;
switch(Data[0] & 0x07)
{
case 0x01:
case 0x02:
case 0x05:
if (MODE_VIDEO50HZ != ucMode_Curr)
ucMode_Curr = MODE_NOSIGNAL;
break;
case 0x00:
case 0x03:
case 0x04:
case 0x06:
if (MODE_VIDEO60HZ != ucMode_Curr)
ucMode_Curr = MODE_NOSIGNAL;
break;
} //switch
}//if
else
{
ucMode_Curr = MODE_NOSIGNAL;
}
// Check result
if (MODE_NOSIGNAL == ucMode_Curr)
{
Reset_Mode();
}
else
{
bStable = 1; // Set bStable to 1 when signal timing is stable.
LED_GREEN = 0X00;
LED_RED = 0X01;
}
#endif
#if (VIDEO_CHIP == VDC_SAA7114 || VIDEO_CHIP == VDC_SAA7115 )
I2CRead(ADDR_VIDEO, 0x1f, 0x01);
// Check color
if (0 == (ucAV_Mode & 0x80))
{
if (0 == (Data[0] & 0x01)) ucMode_Curr = MODE_NOSIGNAL; // Color standard changed
}
else
{
if (0 == (Data[0] & 0x01))
{
ucMode_Times = 0;
}
else
{
// When we cannot lock color, we set color standard to PAL-BDGHI if field rate is 50Hz,
// and to NTSC-M if it is 60Hz.
// If we find color is locked, we should update ucAV_Mode to indicate we now get color.
if (VIDEO_SEARCH_TIMES < ++ucMode_Times) ucAV_Mode = ucAV_Mode & 0x0f;
}
}
// Check field rate
if (Data[0] & 0x40)
{
ucMode_Curr = MODE_NOSIGNAL;
}
else
{
if (ucAV_Mode & 0x02) // 50Hz
{
if (0x00 != (Data[0] & 0x20)) ucMode_Curr = MODE_NOSIGNAL;
}
else // 60Hz
{
if (0x00 == (Data[0] & 0x20)) ucMode_Curr = MODE_NOSIGNAL;
}
}
// Check result
if (MODE_NOSIGNAL == ucMode_Curr)
Reset_Mode();
else
bStable = 1; // Set bStable to 1 when signal timing is stable.
#endif
}
#if (VDC_NONE != VIDEO_CHIP)
void Set_Video_Mode(void)
{
#if (VIDEO_CHIP == TW_9905 )
/*switch(ucAV_Mode)
{
case 1: //NTSC
I2CWrite_TW990X(0x03,0x82);
I2CWrite_TW990X(0x08,0x02); //V delay
I2CWrite_TW990X(0x0a,0x01); //H delay
I2CWrite_TW990X(0x07,0x12); //V,H hi 8~9
I2CWrite_TW990X(0x09,0x40); //V active l
I2CWrite_TW990X(0x0b,0xd0); //H active l
I2CWrite_TW990X(0x19,0x58);
I2CWrite_TW990X(0x55,0x10);
break;
case 2: //PAL
I2CWrite_TW990X(0x03,0x82);
I2CWrite_TW990X(0x08,0x02); //V delay
I2CWrite_TW990X(0x0a,0x01); //H delay
I2CWrite_TW990X(0x07,0x12); //V,H hi 8~9
I2CWrite_TW990X(0x09,0x40); //V active l
I2CWrite_TW990X(0x0b,0xd0); //H active l
I2CWrite_TW990X(0x19,0x58); //
I2CWrite_TW990X(0x55,0x10);
break;
}*/
#endif
#if (VIDEO_CHIP == VDC_SAA7114 || VIDEO_CHIP == VDC_SAA7115 )
I2CWrite(V_DISABLE);
I2CWrite(VIDEO_ALL);
I2CWrite((ucAV_Mode & 0x02) ? VIDEO_50 : VIDEO_60);
#endif
RTDCodeW((ucAV_Mode & 0x02) ? RTD_VIDEO_50 : RTD_VIDEO_60);
if (PANEL_OFF == bPANEL_PWR)
{
RTDSetByte(VDIS_SIGINV_21, 0x00); // DHS, DVS, DEN, DCLK MUST NOT be inverted.
RTDSetBit(VDIS_CTRL_20, 0xfd, 0x01); // DHS, DVS, DEN, DCLK and data are clamped to 0
}
#if (VIDEO_CHIP == TW_9905 )
#endif
#if (VIDEO_CHIP == VDC_SAA7114 || VIDEO_CHIP == VDC_SAA7115 )
Data[0] = (SOURCE_SV == (stGUD1.INPUT_SOURCE & 0x07)) ? 0 : 1;
switch (ucAV_Mode)
{
case 0x01: //(60Hz) NTSC-M, JAPAN(7111A)
case 0x81: //(60Hz) Default
I2CWrite(Data[0] ? AV_60_0 : SV_60_0);
break;
case 0x11: //(60Hz) PAL-4.43
I2CWrite(Data[0] ? AV_60_1 : SV_60_1);
break;
case 0x21: //(60Hz) NTSC-4.43
I2CWrite(Data[0] ? AV_60_2 : SV_60_2);
break;
case 0x31: //(60Hz) PAL-M
I2CWrite(Data[0] ? AV_60_3 : SV_60_3);
break;
case 0x41: //(60Hz) NTSC-JAPAN(7114)
I2CWrite(Data[0] ? AV_60_4 : SV_60_4);
break;
case 0x02: //(50Hz) PAL-BGHI
case 0x82: //(50Hz) Default
I2CWrite(Data[0] ? AV_50_0 : SV_50_0);
break;
case 0x12: //(50Hz) NTSC-4.43
I2CWrite(Data[0] ? AV_50_1 : SV_50_1);
break;
case 0x22: //(50Hz) PAL-N
I2CWrite(Data[0] ? AV_50_2 : SV_50_2);
break;
case 0x32: //(50Hz) NTSC-N
I2CWrite(Data[0] ? AV_50_3 : SV_50_3);
break;
case 0x42: //Reserved
I2CWrite(Data[0] ? AV_50_4 : SV_50_4);
break;
case 0x03: //(50Hz) SECAM
I2CWrite(Data[0] ? AV_SECAM : SV_SECAM);
break;
default:
break;
}
#endif
}
#endif
void Initial_Mode(void)
{
unsigned char ucOption;
unsigned int usDispLen;
// bit 7 of ucMode_Curr : partial-V display.
// bit 6 of ucMode_Curr : select 720x350 or 720x400 for VGA-50Hz and VGA-60Hz
ucOption = ucMode_Curr & 0xc0;
ucMode_Curr = ucMode_Curr & 0x3f;
RTDSetBit(SD_CTRL_70, 0xf9, VGA_ICLK_DELAY);
if (ucOption & 0x40)
{
// Only VGA-50Hz and VGA-60Hz mode will set bit 6 of ucMode_Curr to indicate 720-pixel capture width
// In these case, we should use 720 horizontal settings instead of 640 horizontal settings in table.
usADC_Clock = CAP_WIN[MODE_0720x0400x70HZ][0];
usIPH_ACT_STA = CAP_WIN[MODE_0720x0400x70HZ][1];
usIPH_ACT_WID = CAP_WIN[MODE_0720x0400x70HZ][2];
}
else
{
usADC_Clock = CAP_WIN[ucMode_Curr][0];
usIPH_ACT_STA = CAP_WIN[ucMode_Curr][1];
usIPH_ACT_WID = CAP_WIN[ucMode_Curr][2];
// Calculate pixel clock rate (round to MHz)
usDispLen = (unsigned long)24576 * usADC_Clock / ((unsigned long)usHsync * 500);
usDispLen = (usDispLen >> 1) + (usDispLen & 0x01);
// Use ADC to do H scale-down if pixel clock rate is over spec.
if (MAX_ADC_FREQ < usDispLen && MODE_USER1152x864 <= ucMode_Curr && MODE_USER1600x1200 >= ucMode_Curr)
{
usADC_Clock = ADC_SD_SET[ucMode_Curr - MODE_USER1152x864][0];
usIPH_ACT_STA = ADC_SD_SET[ucMode_Curr - MODE_USER1152x864][1];
usIPH_ACT_WID = ADC_SD_SET[ucMode_Curr - MODE_USER1152x864][2];
}
}
// Calculate pixel clock rate (round to MHz)
usDispLen = (unsigned long)24576 * usADC_Clock / ((unsigned long)usHsync * 500);
usDispLen = (usDispLen >> 1) + (usDispLen & 0x01);
// To improve ADC performance ,when the data rate is slow, use single channel,otherwise, use dual channel
RTDSetBit(ADC_REG_CLK_EA,0x0f,(39 > usDispLen) ? 0x10 | ADC_RED_PHASE_FT | ADC_BLUE_PHASE_FT :
0x00 | ADC_RED_PHASE_FT | ADC_BLUE_PHASE_FT);
// To imporve the FIFO efficiency only when input data rate is slow, and display data rate is high.
// RTDSetBit(VGIP_CTRL_04, 0xe3, (40 > usDispLen) ? 0x14 : 0x00);
RTDSetBit(VGIP_CTRL_04, 0xf3, (40 > usDispLen) ? 0x08 : 0x00);
RTDSetByte(PE_CONTROL_3C, 0x00); // HSYNC positive/negtive tracking
/*
if (60 > usDispLen)
{
RTDSetByte(ADC_REG_CUR_L_E7, 0x6b);
RTDSetByte(ADC_REG_CUR_H_E8, 0x3d);
}
else if (68 > usDispLen)
{
RTDSetByte(ADC_REG_CUR_L_E7, 0x6a);
RTDSetByte(ADC_REG_CUR_H_E8, 0x3d);
}
else if (100 > usDispLen)
{
RTDSetByte(ADC_REG_CUR_L_E7, 0x68);
RTDSetByte(ADC_REG_CUR_H_E8, 0x3d);
}
else if (120 > usDispLen)
{
RTDSetByte(ADC_REG_CUR_L_E7, 0x68);
RTDSetByte(ADC_REG_CUR_H_E8, 0x01);
}
else
{
RTDSetByte(ADC_REG_CUR_L_E7, 0x68);
RTDSetByte(ADC_REG_CUR_H_E8, 0x40);
}
RTDSetByte(ADC_REG_TEST_E9, 0x10);
RTDSetByte(ADC_REG_CUR_H_E8, 0x05);
// Set ADC bandwidth to reduce high frequency noise
RTDSetByte(ADC_REG_TEST_E9, (35 > usDispLen) ? 0x08 : (150 > usDispLen) ? 0x10 : 0x18);
*/
RTDSetByte(ADC_REG_CUR_L_E7, 0x69);
RTDSetByte(ADC_REG_CUR_H_E8, 0x0d | ADC_GREEN_PHASE_FT);
if(ucMode_Curr < MODE_1024x0768x70HZ)
RTDSetByte(ADC_REG_TEST_E9, 0x08);
else
RTDSetByte(ADC_REG_TEST_E9, 0x10);
// Get usIPV_ACT_LEN
if (MODE_UNDEFINED0 > ucMode_Curr)
{
// We've already decided usIPV_ACT_LEN in Detect_VGA_Mode() for undefined SU/SD mode.
// Only defined modes need to decide usIPV_ACT_LEN here.
usIPV_ACT_LEN = CAP_WIN[ucMode_Curr][4];
}
// Get standard usIPV_ACT_STA
RTDSetByte(IVS_DELAY_8C, PROGRAM_VDELAY);
usIPV_ACT_STA = CAP_WIN[ucMode_Curr][3] - PROGRAM_VDELAY - 1;
RTDSetByte(IHS_DELAY_8D, PROGRAM_HDELAY);
usIPH_ACT_STA = usIPH_ACT_STA + CAPTURE_HDELAY - PROGRAM_HDELAY;
// Decide display length (height) and store to usDispLen
usDispLen = Mode_Preset[ucMode_Curr][2];
if (MODE_UNDEFINED0 == ucMode_Curr) // partical-screen scale-up mode
{
if (ucOption & 0x80) // partial-V
{
if (MIN_DV_TOTAL > (usVsync - 1))
usDispLen = (unsigned long)usIPV_ACT_LEN * MIN_DV_TOTAL / (usVsync - 1);
else
usDispLen = usIPV_ACT_LEN; // No V scale-up
}
}
else if (MODE_UNDEFINED1 == ucMode_Curr) // partial-screen scale-down mode
{
if (ucOption & 0x80) // partial-V
{
usDispLen = (unsigned long)usIPV_ACT_LEN * MIN_DV_TOTAL / (usVsync - 1);
}
}
if (Mode_Preset[ucMode_Curr][2] < usDispLen) usDispLen = Mode_Preset[ucMode_Curr][2];
// This F/W do not support V scale-up(or bypass) and H scale-down simultaneously
if (usDispLen >= usIPV_ACT_LEN && Mode_Preset[ucMode_Curr][1] < usIPH_ACT_WID)
{
usIPH_ACT_WID = Mode_Preset[ucMode_Curr][1];
}
if (usDispLen > usIPV_ACT_LEN) ucOption |= 0x01; // bit 0 : V scale-up
if (usDispLen < usIPV_ACT_LEN) ucOption |= 0x02; // bit 1 : V scale-down
if (Mode_Preset[ucMode_Curr][1] > usIPH_ACT_WID) ucOption |= 0x04; // bit 2 : H scale-up
if (Mode_Preset[ucMode_Curr][1] < usIPH_ACT_WID) ucOption |= 0x08; // bit 3 : H scale-down
// Set capture window
Data[0] = 11;
Data[1] = Y_INC;
Data[2] = IPH_ACT_STA_06;
Data[3] = (unsigned char)usIPH_ACT_STA;
Data[4] = (unsigned char)(usIPH_ACT_STA >> 8);
Data[5] = (unsigned char)usIPH_ACT_WID;
Data[6] = (unsigned char)(usIPH_ACT_WID >> 8);
Data[7] = (unsigned char)usIPV_ACT_STA;
Data[8] = (unsigned char)(usIPV_ACT_STA >> 8);
Data[9] = (unsigned char)usIPV_ACT_LEN;
Data[10] = (unsigned char)(usIPV_ACT_LEN >> 8);
Data[11] = 0;
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