📄 _m150xs03.h
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///////////////////////////////////////////////////////////////////
// Definitions for Display Port
#define SINGLE_PORT 0x00 // Single port (Single pixel output)
#define DOUBLE_PORT 0x04 // Double port (Double pixel output)
#define DISPLAY_PORT DOUBLE_PORT
///////////////////////////////////////////////////////////////////
// Definitions for Display Color
#define DISP_18BIT 0x10 // 18-bit RGB output
#define DISP_24BIT 0x00 // 24-bit RGB output
#define DISP_BIT DISP_18BIT
///////////////////////////////////////////////////////////////////
// Definitions for Display Timing Feature
#define MASK_FIRST_DHS 0x80 // Mask 1st DHS
#define NO_MASKING 0x00 // No masking
#define DHS_MASK NO_MASKING
///////////////////////////////////////////////////////////////////
// Definitions for Display Signal
#define DISP_INV 0x0C // DVS : neg , DHS : neg , DEN : pos
#define DCLK_INV 0x00 // DCLK : pos
#define DCLK_DELAY 0x05 // 1.0ns delay for DCLK
///////////////////////////////////////////////////////////////////
// Definitions for Display Settings
#define MAX_DCLK 94 // Maximum display clock rate in MHz that panel can support
#define MAX_RATE 78 // Maximum display refresh rate in Hz that panel can support
#define DH_ACT_STA_POS 0x0022 // DH_ACT_STA_POS should be as small as possible !!!
#define DH_ACT_END_POS 0x0422
#define DV_ACT_STA_POS 0x0011 // DV_ACT_STA_POS should be as small as possible !!!
#define DV_ACT_END_POS 0x0311
#define DISP_WID (DH_ACT_END_POS - DH_ACT_STA_POS) // 0x0500 = 1280 pixels
#define DISP_LEN (DV_ACT_END_POS - DV_ACT_STA_POS) // 0x0400 = 1024 lines
#define STD_DH_TOTAL 0x04a0 // Standard display clock number in one display horizontal line
#define STD_DV_TOTAL 0x0360 // Standard display horizontal line in one display frame
#define STD_HSYNC_WIDTH 0x10 // Display HSYNC clock width
#define STD_VSYNC_LENGTH 0x03 // Display VSYNC line length
#define MIN_DV_TOTAL 0x310 // Minimum VSYNC that panel can support
#define MIN_LAST_DHT 0x00 // Must set to 0 if you don't care last-line length
#define MAX_LAST_DHT 0x00 // Set it to 0 if you don't care the maximum last-line length
#define VIDEO_ML_DHT 0x00 // Minimum last-line length for video
#define USER_MODE_NCODE 20 // NEVER change this setting !!!
#define DISP_ALIGN 0 // 0-Left alignment, 1-Right alignment
#define AUTO_SWITCH 0x60 // Auto Switch to freerun mode
/////////////////////////////////////////////////////////////////// //V212
// Definitions for display size and type
#define DISP_480x234 0 // 0: 480x234
#define DISP_640x480 1 // 1: 640X480
#define DISP_800x600 2 // 2: 800x600
#define DISP_1024x768 3 // 3: 1024x768
#define DISP_1280x768 4 // 4: 1280x768
#define DISP_1280x800 5 // 5: 1280x800
#define DISP_1280x1024 6 // 6: 1280X1024
#define DISP_1400x1050 7 // 7: 1400X1050
#define DISP_1680x1050 8 // 8: 1680X1050
#define DISP_1600x1200 9 // 9: 1280X1024
#define DISP_SIZE DISP_1024x768
#define PANEL_2E 0 // 1 DV_TOTAL_H_2E = 0 0 DV_TOTAL_H_2E != 0
#define TTL_TYPE 0
#define LVDS_TYPE 1
#define RSDS_TYPE 2
#define OUTPUT_BUS TTL_TYPE
#define SWAP_RED_BLUE 0 // 0 : Normal; 1 : Swap Red and Blue
#define SWAP_ODD_EVEN 0 // 0 :83-93 1 : A3-B3
//---------------------------------- 1024x768 ---------------------------------
///////////////////////////////////////////////////////////////////////////
#ifdef __MAIN__
unsigned char code RTD_PWUP_INI[] =
{
5, Y_INC, HOSTCTRL_02, 0x42,0x00,
4, N_INC, TC_ADDR_PORT_95, 0x00,
7, N_INC, TC_DATA_PORT_96, 0x00,0x00,0x00,0x00,
9, Y_INC, GP1_ODOCTRL_F6, 0x00,0x00,0x00,0x00,0x00,0x00,
6, Y_INC, IRQ_CTRL1_0E, 0x00,0x80,0x00,
4, N_INC, INT_FLD_DETECT_14, 0x00,
25, Y_INC, DH_TOTAL_22, 0x08,0x00,0x02,0x04,0x00,0x04,0x00,0x06,0x00,0x06,0x00,
0x06,0x00,0x01,0x02,0x00,0x02,0x00,0x04,0x00,0x04,0x00,
6, Y_INC, YUV2RGB_39, 0x00,0x00,0x00,
5, Y_INC, DUTY_FINE_TUNE_3E, 0xc0,0x0e, // For improving display speed
4, N_INC, MEAS_HS_LATCH_4E, 0x00,
5, Y_INC, CLAMP_55, 0x04,0x10,
4, N_INC, COLOR_CTRL_5D, 0x03,
4, N_INC, OP_CRC_CTRL_68, 0x88,
#if(SWAP_ODD_EVEN) //V212
#if (SWAP_RED_BLUE)
6, Y_INC, PATTERN_GEN_6C, 0x00,0xB3,0x00,
#else
6, Y_INC, PATTERN_GEN_6C, 0x00,0xA3,0x00,
#endif
#else
#if (SWAP_RED_BLUE)
6, Y_INC, PATTERN_GEN_6C, 0x00,0x93,0x00,
#else
6, Y_INC, PATTERN_GEN_6C, 0x00,0x83,0x00,
#endif
#endif //#if(SWAP_ODD_EVEN)
4, N_INC, SD_CTRL_70, 0x00,
6, Y_INC, IVS_DELAY_8C, 0x00,0x00,0x00,
5, Y_INC, TC_ADDR_PORT_95, 0x0E,0x00, //TCON0_REV
5, Y_INC, TC_ADDR_PORT_95, 0x38,0x00, //TCON6_CPV //YCLK
5, Y_INC, TC_ADDR_PORT_95, 0x39,0x30,
5, Y_INC, TC_ADDR_PORT_95, 0x3A,0x13,
5, Y_INC, TC_ADDR_PORT_95, 0x3B,0x00,
5, Y_INC, TC_ADDR_PORT_95, 0x3C,0x10,
5, Y_INC, TC_ADDR_PORT_95, 0x3D,0x00,
5, Y_INC, TC_ADDR_PORT_95, 0x3E,0x80,
5, Y_INC, TC_ADDR_PORT_95, 0x28,0x00, //TCON4_LOAD //XSTB
5, Y_INC, TC_ADDR_PORT_95, 0x29,0x30,
5, Y_INC, TC_ADDR_PORT_95, 0x2A,0X13,
5, Y_INC, TC_ADDR_PORT_95, 0x2B,0x00,
5, Y_INC, TC_ADDR_PORT_95, 0x2C,0x00,
5, Y_INC, TC_ADDR_PORT_95, 0x2D,0x60,
5, Y_INC, TC_ADDR_PORT_95, 0x2E,0x80,
5, Y_INC, TC_ADDR_PORT_95, 0x30,0x10, //TCON5_STH //XDIO
5, Y_INC, TC_ADDR_PORT_95, 0x31,0x30,
5, Y_INC, TC_ADDR_PORT_95, 0x32,0X11,
5, Y_INC, TC_ADDR_PORT_95, 0x33,0x23,
5, Y_INC, TC_ADDR_PORT_95, 0x34,0x00,
5, Y_INC, TC_ADDR_PORT_95, 0x35,0x25,
5, Y_INC, TC_ADDR_PORT_95, 0x36,0x80,
5, Y_INC, TC_ADDR_PORT_95, 0x40,0x00, //TCON7_POL //XPOL
5, Y_INC, TC_ADDR_PORT_95, 0x41,0x30,
5, Y_INC, TC_ADDR_PORT_95, 0x42,0X13,
5, Y_INC, TC_ADDR_PORT_95, 0x43,0x00,
5, Y_INC, TC_ADDR_PORT_95, 0x44,0x00,
5, Y_INC, TC_ADDR_PORT_95, 0x45,0x01,
5, Y_INC, TC_ADDR_PORT_95, 0x46,0x88,
5, Y_INC, TC_ADDR_PORT_95, 0x48,0x00, //TCON8_OE //YOE
5, Y_INC, TC_ADDR_PORT_95, 0x49,0x30,
5, Y_INC, TC_ADDR_PORT_95, 0x4A,0X13,
5, Y_INC, TC_ADDR_PORT_95, 0x4B,0x20,
5, Y_INC, TC_ADDR_PORT_95, 0x4C,0x40,
5, Y_INC, TC_ADDR_PORT_95, 0x4D,0x20,
5, Y_INC, TC_ADDR_PORT_95, 0x4E,0x80,
5, Y_INC, TC_ADDR_PORT_95, 0x50,0x10, //TCON9_STV1 //YDIO1
5, Y_INC, TC_ADDR_PORT_95, 0x51,0x00,
5, Y_INC, TC_ADDR_PORT_95, 0x52,0x12,
5, Y_INC, TC_ADDR_PORT_95, 0x53,0x9F,
5, Y_INC, TC_ADDR_PORT_95, 0x54,0x22,
5, Y_INC, TC_ADDR_PORT_95, 0x55,0xa1,
5, Y_INC, TC_ADDR_PORT_95, 0x56,0x88,
5, Y_INC, TC_ADDR_PORT_95, 0x58,0x11, //TCON10_STV2 //YDIO2
5, Y_INC, TC_ADDR_PORT_95, 0x59,0x00,
5, Y_INC, TC_ADDR_PORT_95, 0x5A,0x13,
5, Y_INC, TC_ADDR_PORT_95, 0x5B,0x9E,
5, Y_INC, TC_ADDR_PORT_95, 0x5C,0x22,
5, Y_INC, TC_ADDR_PORT_95, 0x5D,0xa0,
5, Y_INC, TC_ADDR_PORT_95, 0x5E,0x8A,
//--------------------------------------------------- 9.1
5, Y_INC, TC_ADDR_PORT_95, 0x00,0x04, // OCLK Drive Current
5, Y_INC, TC_ADDR_PORT_95, 0x01,0x74, // ECLK Drive Current 2mA
5, Y_INC, TC_ADDR_PORT_95, 0x02,0x33, // Dispaly Data Drive Current (4 : 8mA)
5, Y_INC, TC_ADDR_PORT_95, 0x03,0x00, //
7, Y_INC, PLL_DIV_CTRL0_C8, 0x04,0x00,0x20,0x18,
8, Y_INC, DPLL_CTRL_D0, 0x10,0x68,0x52,0x2f,0x06, // DCLK=72.5MHz
13, Y_INC, PLL1_CTRL_D6, 0xf2,0x11,0x00,0x7f,0x30,0x0a,0x04,0x3f,0xff,0x81,
4, N_INC, ADC_CTRL_E6, 0xb0,
0
};
unsigned char code RTD_DISABLE_TCON[] =
{
5, Y_INC, TC_ADDR_PORT_95, 0x0E,0x00, //TCON0_REV
5, Y_INC, TC_ADDR_PORT_95, 0x1E,0x00,
5, Y_INC, TC_ADDR_PORT_95, 0x3E,0x00,
5, Y_INC, TC_ADDR_PORT_95, 0x2E,0x00,
5, Y_INC, TC_ADDR_PORT_95, 0x36,0x00,
5, Y_INC, TC_ADDR_PORT_95, 0x46,0x00,
5, Y_INC, TC_ADDR_PORT_95, 0x4E,0x00,
5, Y_INC, TC_ADDR_PORT_95, 0x56,0x00,
5, Y_INC, TC_ADDR_PORT_95, 0x5E,0x00,
0
};
unsigned char code RTD_ENABLE_TCON[] =
{
5, Y_INC, TC_ADDR_PORT_95, 0x0E,0x80, //TCON0_REV
5, Y_INC, TC_ADDR_PORT_95, 0x1E,0x80,
5, Y_INC, TC_ADDR_PORT_95, 0x3E,0x80, //TCON6_CPV
5, Y_INC, TC_ADDR_PORT_95, 0x2E,0x80,
5, Y_INC, TC_ADDR_PORT_95, 0x36,0x80,
5, Y_INC, TC_ADDR_PORT_95, 0x46,0x88,
5, Y_INC, TC_ADDR_PORT_95, 0x4E,0x80,
5, Y_INC, TC_ADDR_PORT_95, 0x56,0x88,
5, Y_INC, TC_ADDR_PORT_95, 0x5E,0x8A,
0
};
unsigned char code RTD_DDC_TABLE[] =
{
5, Y_INC, DDC_ENABLE_FC, 0x00,0x00, // Disable the DDC channel
131, N_INC, DDC_ACCESS_P_FE, 0x00,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0x00,
0x4A,0x8B,0x01,0x00,0x01,0x01,0x01,0x01,
0x0C,0x0F,0x01,0x03,0x6E,0x1E,0x14,0x78,
0xE8,0xCA,0x01,0x9A,0x58,0x52,0x8B,0x28,
0x1E,0x50,0x54,0xAD,0xCE,0x00,0x01,0x01,
0x01,0x01,0x01,0x01,0x01,0x01,0x01,0x01,
0x01,0x01,0x01,0x01,0x01,0x01,0x64,0x19,
0x00,0x40,0x41,0x00,0x26,0x30,0x10,0x88,
0x36,0x00,0x67,0x1F,0x11,0x00,0x00,0x38,
0x00,0x00,0x00,0xFC,0x00,0x4C,0x43,0x44,
0x20,0x31,0x35,0x0A,0x0A,0x0A,0x0A,0x0A,
0x0A,0x0A,0x00,0x00,0x00,0xFD,0x00,0x3A,
0x4B,0x1E,0x41,0x0B,0x00,0x0A,0x20,0x20,
0x20,0x20,0x20,0x20,0x00,0x00,0x00,0x10,
0x00,0x30,0x30,0x30,0x30,0x30,0x31,0x0A,
0x20,0x20,0x20,0x20,0x20,0x20,0x00,0xC1,
4, N_INC, DDC_ENABLE_FC, 0x05, // Enable the DDC channel
0
};
unsigned char code RTD_IO_INI[] =
{
4, N_INC, TC_ADDR_PORT_95, 0x00,
#if((OUTPUT_BUS == LVDS_TYPE) || (OUTPUT_BUS == TTL_TYPE))
// 7, N_INC, TC_DATA_PORT_96, 0x40,0x20,0x11,0x08,
7, N_INC, TC_DATA_PORT_96, 0x01,0x20,0x22,0x08,
5, Y_INC, TC_ADDR_PORT_95, 0x00,0xc1,
#else
7, N_INC, TC_DATA_PORT_96, 0x02,0x10,0x11,0x88,
5, Y_INC, TC_ADDR_PORT_95, 0x00,0xc2,
#endif
0
};
/*
unsigned char code RTD_IO_INI[] =
{
4, N_INC, TC_ADDR_PORT_95, 0x00,
#if((OUTPUT_BUS == LVDS_TYPE) || (OUTPUT_BUS == RSDS_TYPE))
7, N_INC, TC_DATA_PORT_96, 0x01,0x20,0x33,0x08,
5, Y_INC, TC_ADDR_PORT_95, 0x00,0xc1,
#else
7, N_INC, TC_DATA_PORT_96, 0x02,0x10,0x11,0x88,
5, Y_INC, TC_ADDR_PORT_95, 0x00,0xc1,
#endif
0
};*/
// Be Careful !!
// Display window setting in FreeV[] MUST follow the definition of
// 1. DISP_WID and DISP_LEN
// 2. DH_ACT_STA_POS and DH_ACT_END_POS
// 3. DV_ACT_STA_POS and DV_ACT_END_POS
// 4. Background window must be the same as active window.
unsigned char code FreeV[] =
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